Abstract: Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.

Abstract: Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.

Abstract: By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in the read/write voltages for switching on the parasitic bipolar transistor may be accomplished, while the increased punch-through immunity may allow further scaling of the gate length of the floating body storage transistor.

Abstract: In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation process, while maintaining a desired graded dopant profile at the collector side. Consequently, voltages for reading and writing of the FB storage transistor may be reduced, thereby also reducing the amount of die area consumed by respective boost converters. In addition, reliability of the FB transistor, as well as the retention time, may be increased.