Patents by Inventor Nikhil Kelkar

Nikhil Kelkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10582617
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 3, 2020
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Publication number: 20170325333
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: Intersil Americas LLC
    Inventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER,, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR
  • Patent number: 9717146
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 25, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Publication number: 20130314879
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 28, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR
  • Patent number: 8508052
    Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: August 13, 2013
    Assignee: Intersil Americas Inc.
    Inventors: David B. Bell, Francois Hebert, Nikhil Kelkar
  • Patent number: 8324602
    Abstract: An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Patent number: 8232541
    Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 31, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Patent number: 8206836
    Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: June 26, 2012
    Assignee: Intersil Americas, Inc.
    Inventors: Loyde M. Carpenter, Jr., Randolph Cruz, Nikhil Kelkar
  • Publication number: 20120098090
    Abstract: A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.
    Type: Application
    Filed: March 23, 2011
    Publication date: April 26, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Francois Hebert, Shea Petricek, Nikhil Kelkar
  • Publication number: 20110163434
    Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: David B. Bell, Francois Hebert, Nikhil Kelkar
  • Patent number: 7923300
    Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: April 12, 2011
    Assignee: Intersil Americas Inc.
    Inventors: David B. Bell, Francois Hebert, Nikhil Kelkar
  • Publication number: 20110033724
    Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.
    Type: Application
    Filed: February 3, 2010
    Publication date: February 10, 2011
    Inventors: Loyde M. Carpenter, JR., Randolph Cruz, Nikhil Kelkar
  • Publication number: 20100276701
    Abstract: A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.
    Type: Application
    Filed: November 4, 2009
    Publication date: November 4, 2010
    Inventors: François Hébert, Nikhil Kelkar
  • Publication number: 20100258712
    Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Publication number: 20100258710
    Abstract: An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device.
    Type: Application
    Filed: December 21, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Publication number: 20100259766
    Abstract: Provided herein are optical sensor devices, methods for making the same, and systems including the same. An optical sensor device, according to an embodiment, includes a light detector die and a light source die attached to the same or different die attachment substrates so that there is a space between the light source die and the light detector die. A light transmissive material covers the light detector die, the light source die and at least a portion of the space between the light detector die and the light source die. A groove is formed (e.g., saw, blade or laser cut, or cast) in the light transmissive material between the light detector die and the light source die, and an opaque material is put within the groove to provide a light barrier between the light detector die and the light source die.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Patent number: 7510908
    Abstract: Disclosed is a packaged semiconductor device. The device includes a die with an active surface having a plurality of electrical contacts, a back surface located opposite the active surface, and a plurality of side surfaces. The device also includes a first light blocking protective coating that covers at least a portion of the side surfaces of the die. Also, disclosed is a semiconductor wafer including an active surface and a back surface, the active surface having a multiplicity of electrical contacts. The wafer includes a plurality of channels formed in the active surface of the wafer, the channels being arranged in a grid that effectively divide the wafer into a plurality of dice, each die having a plurality of the electrical contacts; and a light blocking filler material that fills the channels. Further, disclosed is a stamp suitable for applying a light blocking filler material into grooves on a semiconductor wafer.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: March 31, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Hau Thanh Nguyen, Nikhil Kelkar
  • Patent number: 7413927
    Abstract: An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau T. Nguyen, Nikhil Kelkar
  • Patent number: 7301222
    Abstract: An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: November 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau T. Nguyen, Nikhil Kelkar
  • Patent number: 7253078
    Abstract: An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 7, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hau T. Nguyen, Viraj A. Patwardhan, Nikhil Kelkar, Shahram Mostafazadeh