Abstract: An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-biased differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-biased differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: A circuit includes a binary weighted divider having a first set of switches coupled in series between an input node and a feedback node. The first set of switches is configured to set a feedback voltage at the feedback node in response to activating or deactivating respective switches in the first set of switches. A set of compensation switches is coupled to the first set of switches. The set of compensation switches is configured to reduce resistance of one or more of the respective switches in the first set of switches that are activated by activating one or more switches in the set of compensation switches to provide one or more respective parallel current paths for each of the switches in the first set of switches that are activated.

Abstract: An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.

Abstract: A circuit includes a binary weighted divider having a first set of switches coupled in series between an input node and a feedback node. The first set of switches is configured to set a feedback voltage at the feedback node in response to activating or deactivating respective switches in the first set of switches. A set of compensation switches is coupled to the first set of switches. The set of compensation switches is configured to reduce resistance of one or more of the respective switches in the first set of switches that are activated by activating one or more switches in the set of compensation switches to provide one or more respective parallel current paths for each of the switches in the first set of switches that are activated.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-based differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-based differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.