Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.

Abstract: In accordance with the present disclosure, a system and method for a managed BIOS is disclosed. A software for a BIOS in an information handling system is provided on a computer readable medium. A first code, for execution on a central processing unit (CPU), is operable to initiate a connection to a management controller through a controller, send a message to the management controller through the controller, and receive a message from the management controller through the controller in response to a system management interrupt. The first code is also operable to stall a power-on procedure if it is able to determine a plurality of bootable devices before the connection to the management controller is ready. The first code is further operable to stall the power-on procedure before releasing control to an operating system if the management controller is active.

Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.

Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.

Abstract: A method for compact encoding including providing a first value field allocated in a first portion of a memory, wherein a portion of the first value field is utilized to store a fixed-size variable. A most significant zero bit (MSZB) is located in the first value field, and it is determined if the fixed-size variable can be written in a first area without performing an erase operation. The first area includes the N bits following the MSZB in the first value field. The fixed-size variable is written into the first area if the fixed-size variable can be written without performing the erase operation.

Abstract: In accordance with the present disclosure, a system and method for a managed BIOS is disclosed. A software for a BIOS in an information handling system is provided on a computer readable medium. A first code, for execution on a central processing unit (CPU), is operable to initiate a connection to a management controller through a controller, send a message to the management controller through the controller, and receive a message from the management controller through the controller in response to a system management interrupt. The first code is also operable to stall a power-on procedure if it is able to determine a plurality of bootable devices before the connection to the management controller is ready. The first code is further operable to stall the power-on procedure before releasing control to an operating system if the management controller is active.

Abstract: Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

Abstract: A switched power rail monitor compares voltages provided by a switched power rail and a power source to detect a predetermined differential indicative of a fault at the switched power rail. A switched power rail fault is communicated to a power manager to take corrective action, such as cutting off power to information handling system components. In one embodiment, a pair of bipolar junction transistors monitor the voltage differential to send an enable signal if the differential is within limits and a disable signal if the differential exceeds limits.

Abstract: A method for compact encoding including providing a first value field allocated in a first portion of a memory, wherein a portion of the first value field is utilized to store a fixed-size variable. A most significant zero bit (MSZB) is located in the first value field, and it is determined if the fixed-size variable can be written in a first area without performing an erase operation. The first area includes the N bits following the MSZB in the first value field. The fixed-size variable is written into the first area if the fixed-size variable can be written without performing the erase operation.

Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.

Abstract: In a circuit identifier, an electrical circuit includes an output node to output an electrical signal. A resistor device and a capacitor device, electrically in series with the resistor device, receive at least a portion of the electrical signal. A counter device determines a time for the capacitor device to reach a predetermined charge and assigns a value to the time for the capacitor device to reach the predetermined charge. A processor or other system reads the value assigned by the counter device and identifies the capacitor from a predetermined list of capacitors. The identification of the capacitor identifies a revision of the circuit.

Abstract: In a circuit identifier, an electrical circuit includes an output node to output an electrical signal. A resistor device and a capacitor device, electrically in series with the resistor device, receive at least a portion of the electrical signal. A counter device determines a time for the capacitor device to reach a predetermined charge and assigns a value to the time for the capacitor device to reach the predetermined charge. A processor or other system reads the value assigned by the counter device and identifies the capacitor from a predetermined list of capacitors. The identification of the capacitor identifies a revision of the circuit.

Abstract: A switched power rail monitor compares voltages provided by a switched power rail and a power source to detect a predetermined differential indicative of a fault at the switched power rail. A switched power rail fault is communicated to a power manager to take corrective action, such as cutting off power to information handling system components. In one embodiment, a pair of bipolar junction transistors monitor the voltage differential to send an enable signal if the differential is within limits and a disable signal if the differential exceeds limits.

Abstract: Audible noise related to power state transitions of an information handling system processing component, such as the central processing unit, is reduced by randomizing the time between power state transitions. Random power state transitions are managed by an operating system module that tracks the transitions and selects random times for subsequent transitions within a predetermined time range. Alternatively, an arbitrating circuit intercepts power state transition commands and arbitrates their communication at random times. Random power state transitions reduces audible noise by spreading the frequency of the noise-causing power transition events over a wider band.

Abstract: An information handling system is provided which includes a wired network controller fixedly mounted in the system and an optional wireless network card which is pluggably receivable by a connector in the system. The system includes a first indicator for annunciating network activity and a second indicator for annunciating that the link is good as well as its link rate. Status processing logic is situated between the wireless card connector, the network controller and the first and second indicators to permit the wireless card and the network controller to share the first and second indicators.

Abstract: A system and method for selecting a voltage output reference required of a DC-DC converter included in a power supply, the voltage output reference corresponding to an operating state of the power supply load. The method stores data for the voltage output reference required for each of a plurality of operating states of the load in a corresponding register. A control input that identifies an operating state of the load is received. An output of the register is selected in response to the control input. The voltage output reference required for the operating state of the load is generated in response to the selected output from the register. An apparatus for selecting a voltage output reference required by a load with a plurality of operating states includes a plurality of registers. Each of the plurality of registers has a register input and a register output, and is configurable to store data corresponding to a voltage required by the load for each of a plurality of operating states.

Abstract: An information handling system (IHS) employs a power fault protection circuit to protect the IHS from overvoltages which may occur on an information line from a power adapter to the IHS. The system includes a processor coupled to the protection circuit. The circuit is operative in a first mode to decouple an information line from the IHS in response to a disable command and operative in a second mode to decouple the information line from the IHS when a voltage in the information line exceeds a predetermined threshold voltage.