Abstract: A Viterbi decoder is described, having a calculation unit (ACSU) for a Radix-2x trellis which, for each trellis state, adds the respectively associated 2x branch metrics (ZMi) to the already accumulated 2x path metrics (PMM) from 2x predecessor trellis states, and selects those of the 2x path metrics (PMi) which have been determined in this way to be extreme as the new accumulated path metric (PMM) for the addition process in the next period, with said calculation unit containing:

Abstract: The subject matter of the application essentially relates to a matrix array of processor units, each processor unit having, in addition to an arithmetic logic unit and a result register bank, a further arithmetic logic unit, a multiplier/adder unit, a storage unit of a distributed screen section buffer and a local general purpose memory. The processor is distinguished by a high processing speed in conjunction with a small chip area and enables real-time processing even in the case of computation-intensive image processing methods such as 2D convolution, Gabor transformation, Gaussian or Laplacian pyramids, block matching, DCT or MPEG2.