Abstract: This invention relates to an inverter with a lateral bipolar pnp (npn) transistor and a vertical, bipolar npn (pnp) transistor which vertical transistor has at least one collector. The collector of the lateral transistor is connected integrally with the base of the vertical transistor. The emitter of the vertical transistor is connected to one terminal of a supply voltage source, and the emitter of the lateral transistor is connected to the other terminal of the supply voltage source. A resistance is connected between the base of the lateral transistor and the said one terminal of the supply voltage source.The inverter is formed in an integrated circuit which includes a substrate which is preferably a semiconductor on which both a pnp (npn) lateral transistor and an npn (pnp) vertical transistor are formed in an epitaxial layer which has been deposited on the substrate. A portion of the emitter of the vertical transistor forms the base of the lateral transistor.

Abstract: A circuit for producing read-out pulses for storage matrices having MI.sub.1 I.sub.2 S transistors includes a MI.sub.1 I.sub.2 S transistor which is subjected to the same writing processes in the same way as the MI.sub.1 I.sub.2 S transistors of the storage matrix, and a read-out voltage is established by this MI.sub.1 I.sub.2 S transistor.