Patents by Inventor Nikzad Toomarian
Nikzad Toomarian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7514964Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.Type: GrantFiled: March 15, 2006Date of Patent: April 7, 2009Assignee: California Institute of TechnologyInventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad M. Mojarradi, Nikzad Toomarian
-
Publication number: 20070008013Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.Type: ApplicationFiled: March 15, 2006Publication date: January 11, 2007Inventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad Mojarradi, Nikzad Toomarian
-
Patent number: 5952685Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.Type: GrantFiled: February 9, 1996Date of Patent: September 14, 1999Assignee: California Institute of TechnologyInventors: Amir Fijany, Jacob Barhen, Nikzad Toomarian
-
Patent number: 5930781Abstract: A method and apparatus for supervised neural learning of time dependent trajectories exploits the concepts of adjoint operators to enable computation of the gradient of an objective functional with respect to the various parameters of the network architecture in a highly efficient manner. Specifically, it combines the advantage of dramatic reductions in computational complexity inherent in adjoint methods with the ability to solve two adjoint systems of equations together forward in time. Not only is a large amount of computation and storage saved, but the handling of real-time applications becomes also possible. The invention has been applied it to two examples of representative complexity which have recently been analyzed in the open literature and demonstrated that a circular trajectory can be learned in approximately 200 iterations compared to the 12000 reported in the literature. A figure eight trajectory was achieved in under 500 iterations compared to 20000 previously required.Type: GrantFiled: October 27, 1992Date of Patent: July 27, 1999Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Nikzad Toomarian, Jacob Barhen
-
Patent number: 5680515Abstract: The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In another aspect of the invention, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neural network and the state function vector elements are treated as neurons. In a further aspect of the invention, moving target detection is performed by driving the soliton equation with a vector of detector outputs.Type: GrantFiled: September 27, 1995Date of Patent: October 21, 1997Assignee: California Institute of TechnologyInventors: Jacob Barhen, Nikzad Toomarian, Amir Fijany, Michail Zak
-
Patent number: 5508538Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.Type: GrantFiled: November 30, 1993Date of Patent: April 16, 1996Assignee: California Institute of TechnologyInventors: Amir Fijany, Jacob Barhen, Nikzad Toomarian
-
Patent number: 5491650Abstract: The present invention discloses increased bit resolution of a charge coupled device (CCD)/charge injection device (CID) matrix vector multiplication (MVM) processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In addition, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neutral network and the state function vector elements are treated as neurons. Further, moving target detection is performed by driving the soliton equation with a vector of detector outputs.Type: GrantFiled: April 19, 1993Date of Patent: February 13, 1996Assignee: California Institute of TechnologyInventors: Jacob Barhen, Nikzad Toomarian, Amir Fijany, Michail Zak
-
Patent number: 5428710Abstract: A neural network is trained to output a time dependent target vector defined over a predetermined time interval in response to a time dependent input vector defined over the same time interval by applying corresponding elements of the error vector, or difference between the target vector and the actual neuron output vector, to the inputs of corresponding output neurons of the network corrective feedback. This feedback decreases the error and quickens the learning process, so that a much smaller number of training cycles are required to complete the learning process. A conventional gradient descent algorithm is employed to update the neural network parameters at the end of the predetermined time interval. The foregoing process is repeated in repetitive cycles until the actual output vector corresponds to the target vector.Type: GrantFiled: June 29, 1992Date of Patent: June 27, 1995Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Nikzad Toomarian, Jacob Barhen