Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: A single field effect transistor capacitor-less memory device, and method of operating the same, including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transistor and a base. The device further includes a fin structure comprising the source region, the intrinsic channel and the drain region, the fin structure extending outwardly from the base, and a double gate comprising a first gate connected to a first exposed lateral face of the intrinsic channel region for transistor control, and a second gate connected to a second exposed lateral face of the intrinsic channel region to generate a potential well for storing mobile charge carriers permitting memory operation, the first gate and the second gate being asymmetric for asymmetric electrostatic control of the device.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.

Abstract: The present invention relates to a single field effect transistor capacitor-less memory device including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transistor and a base. The device further includes a fin structure comprising the source region, the intrinsic channel and the drain region, the fin structure extending outwardly from the base, and a double gate comprising a first gate connected to a first exposed lateral face of the intrinsic channel region for transistor control, and a second gate connected to a second exposed lateral face of the intrinsic channel region to generate a potential well for storing mobile charge carriers permitting memory operation, the first gate and the second gate being asymmetric for asymmetric electrostatic control of the device. The present invention also relates to a method for operating said device.