Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be electrically independent from the first gate and to adjust threshold voltage of the FinFET. Each of the first and second MTJ devices represent a magnetic storage element and includes at least two ferromagnetic (FM) layers separated by a thin insulating layer forming a tunneling junction. Based on the relative magnetization of the two FM layers, each MTJ device has high and low resistance states. Higher reliability of memory write operation is primarily achieved with the help of FinFET and higher reliability of memory read operation is primarily achieved with increased read margin.

Abstract: A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be electrically independent from the first gate and to adjust threshold voltage of the FinFET. Each of the first and second MTJ devices represent a magnetic storage element and includes at least two ferromagnetic (FM) layers separated by a thin insulating layer forming a tunneling junction. Based on the relative magnetization of the two FM layers, each MTJ device has high and low resistance states. Higher reliability of memory write operation is primarily achieved with the help of FinFET and higher reliability of memory read operation is primarily achieved with increased read margin.

Abstract: A content addressable memory (CAM) cell includes a first storage element for storing a data value, a second storage element for storing the data value, and a compare circuit having first inputs to receive from the first storage element a first complementary data signal indicative of the data value, second inputs to receive from the second storage element a second complementary data signal indicative of the data value, third inputs to receive comparand data, and an output coupled to a match line. The CAM cell allows for simultaneous read and compare operations, as well as simultaneous refresh and compare operations.

Abstract: A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell, a second MTJ element coupled between a second input node and the output node of the CAM cell, and a first match transistor coupled between the match line and ground potential and having a gate coupled to the output node. The logic state of the data bit is represented by the relative resistances of the first and second MTJ elements.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: A method and apparatus for simultaneously performing a plurality of compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes first and second memory cells to store first and second data, and first and second compare circuits coupled respectively to first and second match lines. The first compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive first comparand data, and a third input coupled to the second memory cell. The second compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive second comparand data; and a third input coupled to the second memory cell.

Abstract: A content addressable memory (CAM) cell includes a memory cell storing data values. The memory cell includes a surrounding-gate thyristor and an access transistor. The CAM cell also includes a compare circuit coupled among the memory cell and a match line. The compare circuit receives data and comparand data and affects a logical state of a match line in response to a predetermined relationship between the data and comparand data. The compare circuit includes a first transistor set coupled for conduction state control by signals representative of the data, and a second transistor set coupled for conduction state control by signals representative of the comparand data.

Abstract: A ternary content addressable memory (CAM) cell includes a dynamic random access memory (DRAM) cell storing data values and a DRAM cell storing mask values. The mask values control a masking circuit. The CAM cell also includes a compare circuit coupled among the DRAM cell and the masking circuit. The compare circuit of an embodiment receives data and comparand data and affects a logical state of a match line in response to a predetermined relationship between the data and comparand data. The compare circuit includes a first pair of transistors coupled for conduction state control by the comparand data and a second pair of transistors coupled for conduction state control by the data. The first pair of transistors includes two n-channel transistors. The second pair of transistors includes one n-channel and one p-channel transistor. A sense amplifier couples to the match line to detect changes in match line logical state.

Abstract: A content addressable memory (CAM) that includes a CAM array and a write circuit. The write circuit is coupled the CAM array and has a coding circuit to convert a first value into a second value, and a select circuit to select either the first value or the second value to be stored in the CAM array.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.