Patents by Inventor Niloy Mukherjee
Niloy Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11961877Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.Type: GrantFiled: December 14, 2021Date of Patent: April 16, 2024Assignee: KEPLER COMPUTING INC.Inventors: Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni
-
Patent number: 11955512Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.Type: GrantFiled: December 15, 2021Date of Patent: April 9, 2024Assignee: Kepler Computing Inc.Inventors: Somilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni
-
Patent number: 11942133Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 2, 2021Date of Patent: March 26, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
-
Patent number: 11942365Abstract: The disclosed technology generally relates to semiconductor structures and their fabrication, and more particularly to diffusion barrier structures containing Ti, Si, N and methods of forming same. A method of forming an electrically conductive diffusion barrier comprises providing a substrate in a reaction chamber and forming a titanium silicide (TiSi) region on the substrate by alternatingly exposing the substrate to a titanium-containing precursor and a first silicon-containing precursor. The method additionally comprises forming a titanium silicon nitride (TiSiN) region on the TiSi region by alternatingly exposing the substrate to a titanium-containing precursor, a nitrogen-containing precursor and a second silicon-containing precursor. The method can optionally include, prior to forming the TiSi region, forming a titanium nitride (TiN) region by alternatingly exposing the substrate to a titanium-containing precursor and a nitrogen-containing precursor.Type: GrantFiled: May 31, 2018Date of Patent: March 26, 2024Assignee: Eugenus, Inc.Inventors: Vinayak Veer Vats, M. Ziaul Karim, Bo Seon Choi, Somilkumar J. Rathi, Niloy Mukherjee
-
Patent number: 11908704Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.Type: GrantFiled: February 1, 2022Date of Patent: February 20, 2024Assignee: KEPLER COMPUTING INC.Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, Fnu Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
-
Patent number: 11894417Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.Type: GrantFiled: February 3, 2022Date of Patent: February 6, 2024Assignee: KEPLER COMPUTING INC.Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
-
Patent number: 11894465Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.Type: GrantFiled: February 12, 2021Date of Patent: February 6, 2024Assignee: Google LLCInventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
-
Patent number: 11869928Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 14, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11869843Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11871584Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11871583Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 17, 2021Date of Patent: January 9, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
-
Patent number: 11862517Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11854593Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: September 17, 2021Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
-
Patent number: 11844225Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: December 12, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11844203Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: December 12, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Publication number: 20230395369Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.Type: ApplicationFiled: February 15, 2023Publication date: December 7, 2023Inventors: Sung-Hoon Jung, Niloy Mukherjee, Hee Seok Kim, Kyu Jin Choi, Moonsig Joo, Hae Young Kim, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Somilkumar J. Rathi
-
Patent number: 11839088Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: December 5, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11839070Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.Type: GrantFiled: December 16, 2021Date of Patent: December 5, 2023Assignee: KEPLER COMPUTING INC.Inventors: Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Somilkumar J. Rathi, Amrita Mathuriya, Sasikanth Manipatruni
-
Patent number: 11832537Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.Type: GrantFiled: October 8, 2019Date of Patent: November 28, 2023Assignee: Eugenus, Inc.Inventors: Jae Seok Heo, Jerry Mack, Somilkumar J. Rathi, Niloy Mukherjee
-
Patent number: 11832451Abstract: Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.Type: GrantFiled: August 6, 2021Date of Patent: November 28, 2023Assignee: KEPLER COMPUTING INC.Inventors: Debraj Guhabiswas, Maria Isabel Perez, Jason Y. Wu, James David Clarkson, Gabriel Antonio Paulius Velarde, Niloy Mukherjee, Noriyuki Sato, Amrita Mathuriya, Sasikanth Manipatruni, Ramamoorthy Ramesh