Abstract: A design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example, bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. The connectivity of this physical data base file is checked by first generating a circuit level netlist file for the entire option, and then comparing the circuit level netlist with the physical data base file. In generating the circuit level netlist file, information is obtained from the logic netlist file, as well as from some of the other files created in the design-layout sequence. In addition, basic information from which the circuit level netlist is constructed is obtained from a skeleton file library and a subcircuit library.

Abstract: An improved Emitter-Coupled Logic (ECL) circuit having a voltage comparator circuit connected to an emitter follower output circuit, the emitter follower output circuit includes an npn transistor having an emitter connected through a resistor to a voltage supply, and wherein the emitter follower output circuit produces a current in the resistor during operation of the ECL circuit, an improvement in the emitter follower output circuit including programmable connecting means for connecting the emitter follower output circuit to any one of a plurality of alternative voltage supplies, and maintaining means for maintaining substantially the same level of current in the resistor when the emitter follower output circuit is connected to any one of the plurality of alternative voltage supplies.

Abstract: A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root.

Abstract: A voltage is provided by a master circuit and received by a plurality of slave circuits over a bus. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit coupled to the bus. Each of the slave circuits has a pair of transistors coupled to the bus in an emitter-follower configuration to step down the voltage from the master circuit and to provide a voltage reference. The voltage provided to the bus varies as it propagates through the bus. Accordingly, a plurality of unconnected resistors are formed in the portions of the silicon substrate which contain the master and/or slave circuits. When formed in the master circuit, the resistors are located in the V.sub.bb reference circuit. When formed in the slave circuit, the resistors are located in close proximity to the output transistors.

Abstract: An emitter-coupled multiplexer has all transistors directly controlled by one select signal in parallel with transistors directly controlled by other select signals. Thus, in a 3:1 multiplexer (100), a first select signal (S0) directly controls one transistor (Q13); this transistor is in parallel with another transistor (Q14) which is directly controlled by a second select signal (S1). The second select signal also directly controls another transistor (Q15) in the same network (102). This transistor is in parallel with a transistor directly controlled by an input signal (I1) which is thus masked when the second select signal is activated. The second select signal also controls (at Q16 and Q18) subnetwork selection in another current network (104) of the multiplexer. The disclosed arrangement permits the multiplexer function to be implemented with a reduced transistor count and only two current sources in two-level series gating.

Abstract: A multiplexer with inhibit is implemented so that an active inhibit signal effectively sets the select signals to block all but the selected input signal and effectively masks the selected input signal. In the case of the disclosed emitter-coupled logic 4:1 multiplexer, enable signal controlled transistors (Q24 and Q25) are in parallel with transistors (Q14 and Q15) respectively controlled by the select signals (S0 and S1). Activating the enable signal (EN) effectively selects one input (A3) and blocks the others (A0, A1 and A2). A third enable activated transistor (Q35) is in parallel with the transistor (Q13) controlled by the selected input (A3). The activated enable masks the selected signal to complete the inhibit function. Thus, a standard function is implemented with a reduced free-standing and total transistor count.

Abstract: A two-level series gating complementary output master-slave D-type flip-flop (100) with multiplexed input incorporates a novel current-splitting network (108). The flip-flop includes a master latch (102), a slave latch (104) and a 2:1 multiplexer (106) incorporated into the master latch. The multiplexer includes a pair of matched, emitter-coupled, collector-uncoupled transistors (Q12 and Q13), the bases of which are tied to a reference voltage (VBB2). When a clock pulse (CP) is low, substantial network current flows through both matched transistors. This arrangement allows the circuit function to be implemented with a reduced transistor count and only two current sources. The master latch output (QM) is determined by the voltage at the base of an output transistor (Q21), which voltage is determined by the presence or absence of a current through a load resistor (RL1).