Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.

Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.

Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.

Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.

Abstract: A low power CMOS to ECL level translator especially suitable for use as an output level translator includes a CMOS switch having a P-channel MOSFET transistor and an N-channel MOSFET transistor connected to CMOS voltage levels V.sub.DD and V.sub.SS, an NPN bipolar transistor having a base connected to the output of the CMOS switch through an equalization circuit, a collector connected to ECL potential V.sub.CC, and an emitter connected to an ECL potential V.sub.EE. The ECL output is taken directly from the emitter of the bipolar transistor. The equalization circuit includes a PMOS transistor (or parallel transistor array if a greater size is needed) connected between V.sub.CC and the base of the bipolar transistor, the gate or gates thereof being connected to the output of the CMOS switch; and a second PMOS transistor connected between the base and emitter of the bipolar transistor, the gate thereof being connected to the DATA terminal.