Abstract: Systems, methods, and computer-readable media are provided for determining treatments to apply to plants within control volumes having controlled agricultural environments. Each treatment comprises application of a set of setpoints, choosing a reproduction operation for the treatment, and selecting one or more previous sets from setpoints from one or more previously applied treatments, for use with the chosen reproduction operation.

Abstract: Systems, methods, and computer-readable media are provided for determining treatments to apply to plants within control volumes having controlled agricultural environments. Each treatment comprises application of a set of setpoints, choosing a reproduction operation for the treatment, and selecting one or more previous sets from setpoints from one or more previously applied treatments, for use with the chosen reproduction operation.

Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

Abstract: Embodiments include systems and methods for determining link margins of data communications channels in a communications system. For example, an integrated circuit includes a large number of input/output (I/O) channels, each with a respective receiver system. The receiver system can include equalizer subsystems, that attempt to adapt to their respective channels (e.g., to eliminate inter-symbol interference). Embodiments manipulate filter tap weights in the equalizer subsystems to controllably close its respective data eye until a failure region is detected, indicating that a threshold I/O error rate has been exceeded. Thus, for each channel, the filter tap weights can be allowed to fully adjust to identify fully adapted values, and they can be forced into a failure region to identify failure region values. A link margin for each channel can be derived for each channel according to the difference between the fully adapted and failure region values of the filter tap weights.