Abstract: A microprocessor that handles invalid opcodes via an event-signaling micro-operation is disclosed. The microprocessor comprises a decoder that decodes macroinstructions, including an opcode, into a single microprocessor cycle micro-operation. The decoder detects invalid opcodes and replaces the invalid opcodes with an event-signaling micro-operation that triggers an invalid opcode assist. The invalid opcode assist triggers an invalid opcode exception handler that processes the invalid opcode.

Abstract: Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructions and from complex macroinstructions having a beginning microinstruction equivalent to a microinstruction for a simple macroinstruction. The first decoder also includes apparatus for indicating a beginning address for generating any remaining microinstruction vectors for a complex macroinstruction decoded by the first decoder. The apparatus for increasing the decoding speed of a microprocessor also includes apparatus, coupled to the first decoder, for generating any remaining microinstruction vectors for complex macroinstructions decoded by the first decoder. The apparatus for generating any remaining microinstruction vectors includes apparatus for responding to the apparatus for indicating a beginning address.