Abstract: Computing apparatus (11) includes a plurality of processor cores (12) and a cache (10), which is shared by and accessible simultaneously to the plurality of the processor cores. The cache includes a shared memory (16), including multiple block frames of data imported from a level-two (L2) memory (14) in response to requests by the processor cores, and a shared tag table (18), which is separate from the shared memory and includes table entries that correspond to the block frames and contain respective information regarding the data contained in the block frames.

Abstract: An apparatus (10) includes a first plurality of processor cores (200) and a Central Scheduling/Synchronization Unit (CSU, 110), which is coupled to allocate computing tasks for execution by the processor cores. A second plurality of Distribution Units (DUs, 2000) is arranged in a logarithmic network (1000) between the CSU and the processor cores and configured to distribute the computing tasks from the CSU among the processor cores. Each DU includes an associative task registry (2200) for storing information with regard to the computing tasks distributed to the processor cores by the DU.

Abstract: A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement.

Abstract: A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement.

Abstract: The present invention relates to an architectural development of a monolithic integrated circuit with dual public key cryptographic protected central processing units in a computing device, with large external non-volatile reprogrammable memory enabled to perform cryptographically controlled transactions for identification of persons, computers, and or mobile devices, for controlling access to physical and computational devices, for multivendor monetary transactions, and to serve as a safe depository of data, especially useful for encapsulating applications, programmed and updated by varied entitled programmers such that one or many vendors' applications are mutually exclusive, and virtually unable to corrupt, infringe, change or affect other vendor applications.

Abstract: The present invention relates to an architectural development of a monolithic integrated circuit with dual public key cryptographic protected central processing units in a computing device, with large external non-volatile reprogrammable memory enabled to perform cryptographically controlled transactions for identification of persons, computers, and or mobile devices, for controlling access to physical and computational devices, for multivendor monetary transactions, and to serve as a safe depository of data, especially useful for encapsulating applications, programmed and updated by varied entitled programmers such that one or many vendors' applications are mutually exclusive, and virtually unable to corrupt, infringe, change or affect other vendor applications.

Abstract: A high flow-rate synchronizer/scheduler apparatus for a mutiprocessor system during program run-time, comprises a connection matrix for monitoring and detecting computational tasks which are allowed for execution containing a task map and a network of nodes for distributing to the processors information or computational tasks detected to be enabled by the connection matrix. The network of nodes possesses the capability of decomposing information on a pack of allocated computational tasks into messages of finer sub-packs to be sent toward the processors, as well as the capability of unifying packs of information on termination of computational tasks into a more comprehensive pack. A method of performing the synchronization/scheduling in a multiprocessor system of this apparatus is also described.