Abstract: A transfer-indication storage unit indicates an address and a data length of data to be transferred by a DMA circuit. An expected value table refers to a transfer indication of the transfer-indication storage unit and stores therein expected values of the address and the data length of the data to be transferred. A transfer-monitoring unit retrieves tag data and a data length of data in a bus. Based on the data length and the tag data notified by the transfer-monitoring unit, a table updating unit updates a start address and the data length in the expected value table. A determining unit determines whether the start address, corresponding to the DMA circuit after data transfer, matches with an end address, and further determines whether the data length has become zero.

Abstract: In a data relay device, it is judged whether a destination address of data received from an adapter matches with an address specified for an interruption process. Only data that is judged appropriate is sent to a controller.

Abstract: A data relay device relays a read request from a source device to a destination device and relays data corresponding to the read request from the destination device to the source device. The data relay device monitors elapsed time from a time point at which a read request is relayed to the destination device. When the elapsed time reaches warning time or error time, the data relay device sends a warning message or an error message to the source device.

Abstract: According to an aspect of an embodiment, a data transfer device comprises a plurality of transfer circuits managed by a processor, a request accepting unit, a status information collecting unit and a notification data generating unit. The plurality of transfer circuits each controls transfer of data. The request accepting unit accepts a transfer request from at least one of the plurality of transfer circuits. The status information collecting unit collects status information indicating status of data transfer relating to all of the plurality of transfer circuits, upon acceptance of the transfer request. The notification data generating unit generates notification data including information of the transfer circuit regarding which the request accepting unit has received the transfer request and status information collected by the status information collecting unit. And the notification data generating unit transmits the generated notification data to the processor.

Abstract: In a send engine of a protocol/DMA control circuit, a descriptor control circuit obtains a descriptor, and notifies the information of the descriptor to each circuit. A dummy/padding generation circuit generates a data pattern according to the instruction of the descriptor. A write control circuit performs data transfer using the generated data pattern as a dummy transfer data according to the instruction of the descriptor. The write control circuit also inserts the generated data pattern into the transfer data as a padding data according to the instruction of the descriptor, and performs data transfer.

Abstract: A memory includes a set of sequentially stored data. Each of the data includes a variable-length data and length information indicative of a data length of the variable-length data. An MPU creates a read instruction for reading the set of data. A DMS chip, upon receiving the read instruction, reads length information from the memory, calculates a storage location of subsequent data in the memory, and reads the subsequent data from the first memory. Thus, the DMS chip reads the subsequent data from the memory instead of the MPU thereby reducing load on the MPU.

Abstract: A method of writing data includes receiving a record of a variable-length data format, creating a field-checking code for each field of the record received, creating a block-checking code in units of the fixed-length data for the data received, and writing data by reading the record, assembling fixed length data that includes the field-checking code and the block-checking code by using the field-checking code and the block-checking code, and transferring the data to a cache memory.

Abstract: A data transfer apparatus receives comparison data to be compared with stored data from an external unit, searches data corresponding to the comparison data from among the stored data, and transfers the searched data to the external unit. A control unit generates comparison-condition information for searching predetermined stored data from a data storing memory. A comparison-data storing unit stores the received comparison data. A comparison-condition storing unit stores the generated comparison-condition information. A transfer processing unit transfers the searched stored-data to the external unit.

Abstract: A bus bridge device, which connects a first device executing a first process and a second device executing a second process in response to a request from the first device, includes a notifying unit that notifies, when a result of the second process is received from the second device, the result to the first device. The first device executes, after sending the request, a third process until the result is notified from the notifying unit.

Abstract: According to an aspect of an embodiment, a data transfer device comprises a plurality of transfer circuits managed by a processor, a request accepting unit, a status information collecting unit and a notification data generating unit. The plurality of transfer circuits each controls transfer of data. The request accepting unit accepts a transfer request from at least one of the plurality of transfer circuits. The status information collecting unit collects status information indicating status of data transfer relating to all of the plurality of transfer circuits, upon acceptance of the transfer request. The notification data generating unit generates notification data including information of the transfer circuit regarding which the request accepting unit has received the transfer request and status information collected by the status information collecting unit. And the notification data generating unit transmits the generated notification data to the processor.

Abstract: In a data relay device, it is judged whether a destination address of data received from an adapter matches with an address specified for an interruption process. Only data that is judged appropriate is sent to a controller.

Abstract: A data relay device relays a read request from a source device to a destination device and relays data corresponding to the read request from the destination device to the source device. The data relay device monitors elapsed time from a time point at which a read request is relayed to the destination device. When the elapsed time reaches warning time or error time, the data relay device sends a warning message or an error message to the source device.

Abstract: A transfer-indication storage unit indicates an address and a data length of data to be transferred by a DMA circuit. An expected value table refers to a transfer indication of the transfer-indication storage unit and stores therein expected values of the address and the data length of the data to be transferred. A transfer-monitoring unit retrieves tag data and a data length of data in a bus. Based on the data length and the tag data notified by the transfer-monitoring unit, a table updating unit updates a start address and the data length in the expected value table. A determining unit determines whether the start address, corresponding to the DMA circuit after data transfer, matches with an end address, and further determines whether the data length has become zero.

Abstract: A pointer comparing unit determines whether a value of a writing pointer is identical to a value of a reading pointer. When it is determined that the value of the writing pointer is different from the value of the reading pointer, an inter-memory transfer unit reads data stored in a location where a data transfer apparatus reads transmission data from a transmission ring buffer, transfers the data to a reception memory, and writes the data in a location designated by the reading pointer of a reception ring buffer. When the inter-memory transfer unit completes writing of the data in the reception ring buffer, a reading-pointer updating unit updates the reading pointer.

Abstract: In a send engine of a protocol/DMA control circuit, a descriptor control circuit obtains a descriptor, and notifies the information of the descriptor to each circuit. A dummy/padding generation circuit generates a data pattern according to the instruction of the descriptor. A write control circuit performs data transfer using the generated data pattern as a dummy transfer data according to the instruction of the descriptor. The write control circuit also inserts the generated data pattern into the transfer data as a padding data according to the instruction of the descriptor, and performs data transfer.

Abstract: A memory includes a set of sequentially stored data. Each of the data includes a variable-length data and length information indicative of a data length of the variable-length data. An MPU creates a read instruction for reading the set of data. A DMS chip, upon receiving the read instruction, reads length information from the memory, calculates a storage location of subsequent data in the memory, and reads the subsequent data from the first memory. Thus, the DMS chip reads the subsequent data from the memory instead of the MPU thereby reducing load on the MPU.

Abstract: A data transferring apparatus receives comparison data to be compared with stored data from an external unit, searches data corresponding to the comparison data from among the stored data, and transfers the data searched to the external unit. A control unit generates comparison-condition information for searching predetermined stored data from a data storing memory. A comparison-data storing unit stores the comparison data received. A comparison-condition storing unit stores the comparison-condition information generated, upon the comparison-data storing unit storing the comparison data. A transfer processing unit transfers the stored data searched to the external unit.

Abstract: A pointer comparing unit determines whether a value of a writing pointer is identical to a value of a reading pointer. When it is determined that the value of the writing pointer is different from the value of the reading pointer, an inter-memory transfer unit reads data stored in a location where a data transfer apparatus reads transmission data from a transmission ring buffer, transfers the data to a reception memory, and writes the data in a location designated by the reading pointer of a reception ring buffer. When the inter-memory transfer unit completes writing of the data in the reception ring buffer, a reading-pointer updating unit updates the reading pointer.

Abstract: A data transfer apparatus receives comparison data to be compared with stored data from an external unit, searches data corresponding to the comparison data from among the stored data, and transfers the searched data to the external unit. A control unit generates comparison-condition information for searching predetermined stored data from a data storing memory. A comparison-data storing unit stores the received comparison data. A comparison-condition storing unit stores the generated comparison-condition information. A transfer processing unit transfers the searched stored-data to the external unit.

Abstract: A method of writing data includes receiving a record of a variable-length data format, creating a field-checking code for each field of the record received, creating a block-checking code in units of the fixed-length data for the data received, and writing data by reading the record, assembling fixed length data that includes the field-checking code and the block-checking code by using the field-checking code and the block-checking code, and transferring the data to a cache memory.