Abstract: Methods, systems, and devices for performing an access operation on a memory cell, incrementing a value of a first counter based on performing the access operation on the memory cell, determining that the incremented value of the first counter satisfies a threshold, incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold, and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold are described.

Abstract: An etchant composition, a tackifier, an alkaline solution, a method of removing polyimide and an etching process are provided. The etchant composition includes a tackifier (A) and an alkaline solution (B). The tackifier (A) includes a resin containing a hydroxyl group (a), a surfactant (b) and a first solvent (c1). The alkaline solution (B) includes an alkaline compound (d) and a second solvent (c2).

Abstract: Novel cultivars of Stevia rebaudiana plant, with a novel genetic trait of self-compatibility, and the advantageous use of this genetic trait in Stevia crossing breeding for increasing steviol glycosides production, including food and beverage products and other consumables, are disclosed.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: Systems and methods for pacing data transmission are described. An illustrative method includes transmitting, by a network device, a data stream at a pacing rate to a user equipment (UE) device. The method further includes accessing a metric of a radio access network (RAN) to which the UE device is connected, the metric associated with the UE device. The method further includes adjusting, based on the metric, the pacing rate at which the data stream is transmitted to the UE device.

Abstract: A switching charger for supplying stable power is provided. First input terminals of first and fourth operational amplifiers and a second input terminal of a second operational amplifier are connected to a battery. A second input terminal of the first operational amplifier is coupled to a reference voltage. A first input terminal of the second operational amplifier and a second input terminal of the fourth operational amplifier are connected to an inductor. A first input terminal of a third operational amplifier is connected to an input power source. A second input terminal of the third operational amplifier is connected to a system circuit. A first selector circuit is connected to output terminals of the third and fourth operational amplifiers. A second selector circuit is connected to output terminals of the first and second operational amplifiers and the first selector circuit.

Abstract: A test structure and methods of forming the same are described. In some embodiments, the structure includes a first portion having a first thickness, and the first portion comprises one or more dielectric layers. The test structure further includes a second portion disposed adjacent the first portion, the second portion has a second thickness substantially less than the first thickness, and the second portion includes the one or more dielectric layers and a first plurality of test conductive features disposed in the one or more dielectric layers. The test structure further includes a third portion disposed adjacent the second portion, the third portion has a third thickness substantially less than the second thickness, and the third portion comprises the one or more dielectric layers and a second plurality of test conductive features disposed in the one or more dielectric layers.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.

Abstract: Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

Abstract: A switching charger having fast dynamic response for transition of a load is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A first terminal of an inductor is connected to a node between the first terminal of the low-side switch and the second terminal of the high-side switch. A second terminal of the inductor is connected to a first terminal of a capacitor. A constant on-time circuit determines a duty cycle of an on-time signal according to the input voltage and an output voltage of a node between the second terminal of the inductor and the first terminal of the capacitor. A control circuit controls a driver circuit to drive the high-side switch and the low-side switch according to the on-time signal.

Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.

Abstract: Disclosed is a method for identifying and parsing an industrial control protocol based on an industrial gateway. The industrial gateway captures, through a serial port and a network port, messages sent from a host computer and a lower computer to the industrial gateway, extracts features representing different protocol types and protocol fields from the messages, and identifies and parses the messages based on protocol character features.

Abstract: The use of a mitoxantrone preparation in the preparation of a drug for diagnosing and treating breast cancer. Provided is the use of mitoxantrone and/or a pharmaceutically acceptable salt thereof in the preparation of a lymphatic tracer in a disease associated with breast resection. No local or systemic toxic and side effects are seen after local injection of the preparation, suggesting that the preparation has good tolerance, effectiveness and safety, which provides a new treatment idea for thoroughly curing breast cancer in a breast cancer patient.

Abstract: Disclosed herein is a device for reducing the volume of an aquatic sample, comprising, a substrate; a metal layer disposed above the substrate; a hydrophobic layer disposed above the metal layer having a plurality of assay wells formed therein; and a hydrophilic layer coated on each of the plurality of assay wells. Also encompassed in the present disclosure are a kit comprising the device and a lipoplex containing a liposome and a fluorescence-labeled molecular beacon inside the liposome, and use of the kit in detecting a target nucleic acid in a biological sample.

Abstract: Provided herein are KRAS G12C inhibitors, composition of the same, and methods of using the same. These inhibitors are useful for treating a number of disorders, including pancreatic, colorectal, and lung cancers.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.