Abstract: A processing method and a terminal for random access are provided in the embodiments of the present invention. The method includes: triggering, by a terminal, first random access through Media Access Control (MAC), and successfully accessing a device at a network side; when a Scheduling Request (SR) of the terminal is triggered, determining whether to trigger next random access, where if the next random access is determined not to be triggered, the terminal does not execute the random access; receiving, by the terminal, a Radio Resource Control (RRC) reconfiguration message that carries an SR related parameter and the RRC reconfiguration message is sent by the device at the network side; and determining, according to the SR related parameter, by the terminal, a Physical Uplink Control Channel (PUCCH) resource for sending the SR, and sending the SR by using the PUCCH resource.

Abstract: A random access processing method and User Equipment (UE) are provided in the present invention. The method includes: after receiving current Random Access Response (RAR) information sent from an evolved Node B (eNB), comparing current uplink grant information in the current RAR information with pre-stored uplink grant information, where the pre-stored uplink grant information is uplink grant information in previous RAR information received in a previous random access process; performing data scheduling and packetization according to the current uplink grant information to generate a first data packet carrying a UE identifier when the current uplink grant information is not consistent with the pre-stored uplink grant information; sending the first data packet to the eNB, and receiving a second data packet from the eNB; and parsing the second data packet, and determining whether contention-based random access is successful according to a parsing result.

Abstract: Over the years, parallel processing has become increasingly common. Conventional circuit simulators have not taken full advantage of these developments, however. Here, a circuit simulator and system are provided that partitions circuit matrices to allow for more efficient parallel processing to take place. By doing this, the overall speed and reliability of the circuit simulator can be increased.