Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

Abstract: A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also includes a second path connecting a second series of logic elements in the logic array block, where one or more of the logic elements in the second series are not in the first series.

Abstract: An RTL representation for a LAB is generated. A full chip RTL model is then generated using a plurality of the LAB RTLs. Using the full chip RTL model, a full chip simulation of the PLD chip is performed to verify and debug the electronic design.

Abstract: An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

Abstract: A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit also includes a carry chain connecting the first series of logic element, and an initialization circuit connected to the carry chain to initialize the carry chain.

Abstract: An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.

Abstract: A power-on reset (POR) circuit (200) asserts a POR signal when the supply voltage (V.sub.CC) is turned on. As the supply voltage increases, the POR signal is deasserted when the supply voltage reaches a voltage (V.sub.POR1) sufficiently high to make storage elements in a controlled circuit fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough (V.sub.POR2) to render the storage elements in the controlled circuit incapable of holding accurate data. The V.sub.POR2 level that triggers the reassertion of the POR signal is lower than the V.sub.POR1. Additional circuitry insures that the POR signal is reasserted when V.sub.CC drops to the V.sub.POR2 level by sampling the transistor threshold voltages of the circuit. Another control signal allows the POR signal to be forcibly generated.