Patents by Inventor Nippon Raval

Nippon Raval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12130737
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: October 29, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Nippon Raval, Philip Ng, Rostislav S. Dobrin
  • Publication number: 20240289151
    Abstract: A processor configured to execute one or more virtual machines (VMs) includes an input-output memory management unit (IOMMU) configured to handle memory-mapped input-output (MMIO) requests and direct memory access (DMA) requests from a processor core of the processor or one or more input/output (I/O) devices. In response to receiving an MMIO or DMA request, the IOMMU is configured to determine a VM associated with the request. The IOMMU then checks a security indicator field of an address space identifier (ASID) mask table to determine if the VM was previously the target of an attack by a malicious entity. In response to the VM previously being a target of an attack, the IOMMU denies the received MMIO or DMA request.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Philip Ng, Nippon Raval, Jeremy W. Powell, Donald Matthews, JR., David Kaplan
  • Publication number: 20240289150
    Abstract: A processor includes a security processor and an input-output memory management unit (IOMMU). The security processor is configured to maintain device control information in a secure data structure and prevent a hypervisor from accessing the secure data structure. The IOMMU is configured to process at least one device request targeting a virtual machine from an input/output device based on the secure data structure.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Philip Ng, Nippon Raval, Jeremy W. Powell, Donald Matthews, JR., David Kaplan
  • Publication number: 20240220417
    Abstract: A computing device comprises a processor, a table walker, and a memory storing a segmented reverse map table in multiple non-contiguous portions of the memory. The table walker is configured to translate a virtual memory address specified by a memory access request to a physical memory address associated with the virtual memory address; and provide a requester associated with the memory access request with access to the associated physical memory address in response to an indication at the reverse map table that the requester is authorized to access the associated physical memory address.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: David Kaplan, Jelena Ilic, Nippon Raval, Philip Ng
  • Publication number: 20240220297
    Abstract: Techniques for implementing programmable control by a guest virtual machine (VM) of interrupts at a processing system using a guest owned backing page are disclosed. The VM programs a guest owned backing page (e.g., a data structure in memory) that designates particular interrupts that are to be blocked. In response to detecting a designated interrupt, system hardware or software blocks the interrupt, rather than executing an interrupt handler to process the interrupt. The VM is thereby able to protect confidential information and program behavior with less risk of a malicious hypervisor failing to protect the VM from, e.g., unexpected or unwanted interrupts, thereby improving overall system security and predictability.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: David Kaplan, Jelena Ilic, Nippon Raval, Philip Ng
  • Publication number: 20240220296
    Abstract: A processor manages memory-mapped input/output (MMIO) accesses, in secure fashion, at an input/output memory management unit (IOMMU). The processor is configured to ensure that, for a given MMIO request issued by a processor core and associated with a particular executing VM, the request is targeted to a MMIO address that has been assigned to the VM by a security module (e.g., a security co-processor). The processor thus prevents a malicious entity from accessing confidential information of a VM via MMIO requests.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Philip Ng, Nippon Raval, Jeremy W. Powell, Donald Matthews, JR., David Kaplan
  • Publication number: 20240220429
    Abstract: A processor supports managing DMA accesses, in secure fashion, at an IOMMU. The IOMMU is configured to ensure that, for a given DMA request issued by an I/O device and associated with a particular executing VM, the device is bound to the VM according to a specified security registration process, and the request is targeted to a region of memory that has been assigned to the VM. The IOMMU thus prevents a malicious entity from accessing confidential information of a VM via DMA requests.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Philip Ng, Nippon Raval, Jeremy W. Powell, Donald Matthews, JR., David Kaplan
  • Patent number: 11860797
    Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 2, 2024
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Philip Ng, Nippon Raval, David A. Kaplan, Donald P. Matthews, Jr.
  • Publication number: 20230315625
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: NIPPON RAVAL, PHILIP NG, ROSTISLAV S. DOBRIN
  • Patent number: 11726693
    Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 15, 2023
    Assignee: ATI Technologies ULC
    Inventors: Philip Ng, Nippon Raval
  • Publication number: 20230229603
    Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 20, 2023
    Inventors: PHILIP NG, NIPPON RAVAL, DAVID A. KAPLAN, DONALD P. MATTHEWS, JR.
  • Patent number: 11698860
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 11, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Nippon Raval, Philip Ng, Rostislav S. Dobrin
  • Publication number: 20230214346
    Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventors: NIPPON RAVAL, PHILIP NG, JAROSLAW MARCZEWSKI
  • Patent number: 11567666
    Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 31, 2023
    Assignee: ATI Technologies ULC
    Inventors: Philip Ng, Nippon Raval
  • Patent number: 11550722
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 10, 2023
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
  • Publication number: 20220308756
    Abstract: An electronic device includes an input-output memory management unit (IOMMU). The IOMMU receives, from an input-output device, a memory access request directed to a given page of memory. The IOMMU then determines a particular encryption key from among a plurality of encryption keys associated with an owning entity to which the given page of memory is assigned. The IOMMU next communicates, to a encryption functional block, a specification of the particular encryption key to be used for encryption-related operations for processing the memory access request.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Nippon Raval, Philip Ng
  • Publication number: 20220308755
    Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: Philip Ng, Nippon Raval
  • Publication number: 20220283946
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 8, 2022
    Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
  • Publication number: 20220206700
    Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Philip Ng, Nippon Raval
  • Publication number: 20220206942
    Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: NIPPON RAVAL, PHILIP NG, ROSTISLAV S. DOBRIN