Abstract: A method of enhancing error correction in a data storage system, including receiving a data storage system having one or more rows each row having: a set of data bits including a word of data, a first set of error correction bits and a second set of error correction bits or a flag bit or both; each bit can be in a first state or a second state; wherein initially all the bits are in the first state; writing data in a word in the data storage system by changing bits from the first state to the second state; creating an error correction code for the word and writing it to the first set of error correction bits; when needing to update the word using the second set of error correction bits and/or the flag bit to reduce the need to rewrite the word because of the error correction code.

Abstract: A method of enhancing error correction in a data storage system, including receiving a data storage system having one or more rows each row having: a set of data bits including a word of data, a first set of error correction bits and a second set of error correction bits or a flag bit or both; each bit can be in a first state or a second state; wherein initially all the bits are in the first state; writing data in a word in the data storage system by changing bits from the first state to the second state; creating an error correction code for the word in the first set of error correction bits; receiving a request to update the word by changing one or more additional bits of the word from the first state to the second state; calculating a new error correction code for the updated word; optionally determining if the new error correction code only requires changing bits of the first set of error correction bits from the first state to the second state, if the determination result is positive then updating the fi

Abstract: An Integrated Circuit (IC) includes clock-tree circuitry and protection circuitry. The clock-tree circuitry is configured to distribute a clock signal across the IC. The protection circuitry is clocked by multiple instances of the clock signal that are sampled at multiple sampling points in the clock-tree circuitry, and is configured to detect a fault in the clock-tree circuitry in response to an abnormality in one or more of the instances of the clock signal.

Abstract: An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.

Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

Abstract: A secure data storage device for preventing tampering with data stored thereon includes a two-dimensional memory array for storing data, the array includes a predetermined number of data words. Each data word includes a set of bits, and is associated with a single physical address in the memory array. A key storage area for storing a key of the data storage device is included in the device. The secure data storage device includes an address conversion unit configured to convert a logical address to a corresponding physical address which points to a location in the memory array. The device includes a bit mixing unit for mixing bit values of an input data word to obtain a mixed word value, such that the mixed word value is a rearrangement of the bit values of the input data word. The device is electrically connectable to a host.

Abstract: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

Abstract: An apparatus includes a processor and a bus encryption unit. The processor is configured to communicate information over a secured data bus, and to communicate respective addresses over an address bus. The bus encryption unit is configured to generate an encryption key based on multiple addresses that appeared on the address bus, and to encrypt the information communicated between the processor and the secured data bus with the encryption key.

Abstract: An Integrated Circuit (IC) includes clock-tree circuitry and protection circuitry. The clock-tree circuitry is configured to distribute a clock signal across the IC. The protection circuitry is clocked by multiple instances of the clock signal that are sampled at multiple sampling points in the clock-tree circuitry, and is configured to detect a fault in the clock-tree circuitry in response to an abnormality in one or more of the instances of the clock signal.

Abstract: An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.

Abstract: An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.

Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.

Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

Abstract: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Abstract: A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface.

Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.

Abstract: Methods and systems for Basic Input/Output System BIOS processing such as hashing are disclosed. In one embodiment, there is a direct interface between a security module and a non-volatile memory storing the BIOS in a computing system so that the security module may directly access the BIOS without using the central processing unit CPU as an intermediary. In one embodiment, the security module is powered by standby power and therefore can begin BIOS processing even if the computing system has not yet been turned on.

Abstract: An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.

Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.