Abstract: A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.

Abstract: Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead.

Abstract: Hardware-software co-synthesis of an embedded system requires mapping of its specifications into hardware and software modules such that its real-time and other constraints are met. Embedded system specifications are generally represented by acyclic task graphs. Many embedded system applications are characterized by aperiodic as well as periodic task graphs. Aperiodic task graphs can arrive for execution at any time and their resource requirements vary depending on how their constituent tasks and edges are allocated. Traditional approaches based on a fixed architecture coupled with slack stealing and/or on-line determination of how to serve aperiodic task graphs are not suitable for embedded systems with hard real-time constraints, since they cannot guarantee that such constraints would always be met. The present invention addresses the problem of concurrent co-synthesis of aperiodic and periodic specifications of embedded systems.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: A low-overhead controller-based power management technique that re-specifies control signals to reconfigure existing multiplexer networks and functional units to minimize unnecessary activity. Though the control signals in an RT-level implementation are fully specified, they can be re-specified under certain states/conditions when the data path components that they control need not be active. Another aspect of this invention is an algorithm to perform power management through controller re-specification, that consist of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. The algorithm avoids the above negative effects of controller re-specification.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has a pre-processing phase during which task graphs, system/task constraints, and a resource library for the embedded system are parsed, wherein the resource library has different PEs requiring different power supply voltages.

Abstract: A computer-aided design tool and associated methods address the problem of high-level behavioral synthesis, useful in the design of semiconductor integrated circuit for minimum power consumption. The tool makes a plurality of types of power reducing changes, and evaluates the results using iterative improvement. In a particular embodiment, "moves" corresponding to alterations of scheduling of operations or resource sharing are iteratively proposed and evaluated with a power "cost function" defined by summing estimates of the switched capacitance of each resource element. In an extension of that embodiment, moves corresponding to alterations of module selection and clock selection are also evaluated.