Patents by Inventor Niraj K. Pandey

Niraj K. Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Template-based methodology for validating hardware features
    Patent number: 10248534
    Abstract: In one embodiment of the present invention, a thread is scheduled for execution by a processor, and the thread includes instructions for testing functionality of a feature of the processor. A workload location on the thread is determined. A hook is placed on the determined workload location. The thread is executed by the processor. In response to encountering the hook during the execution of the thread, a workload is selected from a pool, and the pool includes two or more workloads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Purushotam Bheemanna, Niraj K. Pandey
  • TEMPLATE-BASED METHODOLOGY FOR VALIDATING HARDWARE FEATURES
    Publication number: 20180150319
    Abstract: In one embodiment of the present invention, a thread is scheduled for execution by a processor, and the thread includes instructions for testing functionality of a feature of the processor. A workload location on the thread is determined. A hook is placed on the determined workload location. The thread is executed by the processor. In response to encountering the hook during the execution of the thread, a workload is selected from a pool, and the pool includes two or more workloads.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Purushotam Bheemanna, Niraj K. Pandey