Patents by Inventor Niraj VASUDEVAN

Niraj VASUDEVAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reusing manufacturing content across multi-chip packages
    Patent number: 11808811
    Abstract: An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Kalyana Kantipudi, Niraj Vasudevan
  • APPARATUS AND METHOD FOR REUSING MANUFACTURING CONTENT ACROSS MULTI-CHIP PACKAGES
    Publication number: 20230288479
    Abstract: An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Kalyana KANTIPUDI, Niraj VASUDEVAN