Patents by Inventor Nirmal K. Sharma

Nirmal K. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6861283
    Abstract: A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: March 1, 2005
    Assignee: Intersil Corporation
    Inventor: Nirmal K. Sharma
  • Patent number: 6809416
    Abstract: A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Intersil Corporation
    Inventor: Nirmal K. Sharma
  • Publication number: 20040097015
    Abstract: A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 20, 2004
    Inventor: Nirmal K. Sharma
  • Patent number: 6420779
    Abstract: An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: July 16, 2002
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Nirmal K. Sharma, Rahamat Bidin, Hien Boon Tan
  • Patent number: 4731701
    Abstract: An integrated circuit package includes a case incorporating an integrated circuit die. The case has several ceramic layers, including layers with apertures for defining a die cavity and two layers without apertures which serve as thermal path layers. The thermal path layers include mutually staggered vias which conduct heat from the die cavity to a heat spreader separated from the die by the thermal path layers. The vias of the two layers are not electrically coupled so that the heat spreader is thermally coupled and electrically uncoupled with respect to the die. The thermal path layers, the thermal vias and other thermal path elements are fabricated from the same set of materials used in the cavity-defining layers, electrical vias and conductive strips.
    Type: Grant
    Filed: May 12, 1987
    Date of Patent: March 15, 1988
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Marco K. Kuo, Nirmal K. Sharma