Abstract: Examples described herein provide for a technique for metal track routing with buffer bank insertion in a representation of a hardware design of an integrated circuit. In an example, pins of ports of hardblocks in a placed layout are identified. Logical tracks for nets associated with the pins of the ports are generated and assigned to respective metal layers. Logical tracks and corresponding nets are grouped into respective groups. Buffer bank(s) is inserted into the placed layout. Each buffer bank is for a group of logical tracks and divides each logical track and net of the group of logical tracks. Each buffer bank has pins associated with the respective divided nets. Each pin of the buffer bank(s) is assigned to a middle or higher metal layer. Metal tracks are generated in a representation of a hardware layout based on the logical tracks and pins of the ports and buffer bank(s).

Abstract: Embodiments of the present disclosure are directed towards a computer system with cache policy that may be modified in response to temperature changes. In some embodiments, the system may include a memory storage having a first storage device with a first response time, and a second storage device with a second response time that may be higher than the first response time. The system may include a cache policy module to facilitate execution of I/O requests to access the memory storage. The cache policy module may be configured to restrict access to at least a portion of the first storage device and provide access to the second storage device, in response to an increase of temperature of the first storage device above a threshold. Other embodiments may be described and/or claimed.