Patents by Inventor Nishad Udugampola
Nishad Udugampola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9070735Abstract: The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.Type: GrantFiled: July 2, 2013Date of Patent: June 30, 2015Assignee: Cambridge Microelectronics Ltd.Inventors: Vasantha Pathirana, Nishad Udugampola, Tanya Trajkovic
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Publication number: 20150008481Abstract: The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.Type: ApplicationFiled: July 2, 2013Publication date: January 8, 2015Inventors: Vasantha PATHIRANA, Nishad UDUGAMPOLA, Tanya TRAJKOVIC
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Patent number: 8866252Abstract: We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.Type: GrantFiled: September 15, 2011Date of Patent: October 21, 2014Assignee: Cambridge Semiconductor LimitedInventors: Tanya Trajkovic, Florin Udrea, Vasantha Pathirana, Nishad Udugampola
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Patent number: 8482031Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain ?v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT ?v<1??p where ?p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.Type: GrantFiled: December 29, 2009Date of Patent: July 9, 2013Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Patent number: 8415712Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.Type: GrantFiled: December 29, 2009Date of Patent: April 9, 2013Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Publication number: 20130069712Abstract: We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Inventors: Tanya Trajkovic, Florin Udrea, Vasantha Pathirana, Nishad Udugampola
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Patent number: 8174069Abstract: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.Type: GrantFiled: August 5, 2008Date of Patent: May 8, 2012Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Publication number: 20110156096Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Inventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Publication number: 20110057230Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain ?v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT ?v<1??p where ?p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.Type: ApplicationFiled: December 29, 2009Publication date: March 10, 2011Inventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Publication number: 20100032712Abstract: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.Type: ApplicationFiled: August 5, 2008Publication date: February 11, 2010Applicant: Cambridge Semiconductor LimitedInventors: Florin UDREA, Vasantha PATHIRANA, Tanya TRAJKOVIC, Nishad UDUGAMPOLA
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Patent number: 7605446Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.Type: GrantFiled: July 14, 2006Date of Patent: October 20, 2009Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Nishad Udugampola, Gehan A. J. Amaratunga
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Patent number: 7531993Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.Type: GrantFiled: August 29, 2007Date of Patent: May 12, 2009Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Nishad Udugampola, Gehan A. J. Amaratunga
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Publication number: 20090058498Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Applicant: Cambridge Semiconductor LimitedInventors: Florin UDREA, Nishad Udugampola, Gehan Anil Joseph Amaratunga
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Publication number: 20080012043Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.Type: ApplicationFiled: July 14, 2006Publication date: January 17, 2008Applicant: Cambridge Semiconductor LimitedInventors: Florin Udrea, Nishad Udugampola, Gehan A.J. Amaratunga