Abstract: A computerized system and method for dynamically generating modified user interface is disclosed. The method comprises receiving a search request, providing a list of at least one product in response to the search request, receiving a selection of a first product from the user device, providing the first product to the user device for display on the user interface, determining signals of the first product and their weights, calculating a score for each of the second products based on signals of the first product, ranking the second products by the score, and in response to receiving a request to redisplay the list of product, providing, to the user device for display together with the list of product, at least one second product based on the ranking.

Abstract: A communications system may include user equipment (UE) device, satellites, and a gateway. The UE and gateway may perform implicit handover in which the UE and gateway independently identify the same serving satellite using ephemeris data, without additional signaling overhead. The UE may also characterize its channel conditions. When insufficient, the UE may transmit an explicit handover message to the gateway via a different satellite visible to the UE. The explicit handover message may include a satellite identifier and a lock bit. The gateway may use the satellite identifier to convey wireless data with the UE via the different satellite during the next cycle. The gateway may use the lock bit to know how to perform handover away from the different cycle during subsequent cycles. In this way, the UE may direct handover, given that the gateway has no knowledge of the channel condition at the UE.

Abstract: User equipment includes one or more antennas, a receiver coupled to the one or more antennas, and processing circuitry coupled to the receiver and configured to cause the user equipment to receive downlink signals at each communication cycle using a predetermined beam in a beam time slot. Based on processed downlink signals and other relevant information the user equipment may determine a desired beam for the next communication cycle. If the desired beam is the same as the predetermined beam, the user equipment may continue using the predetermined beam at the next communication cycle. If the desired beam is different from the predetermined beam, the user equipment may switch to the desired beam at the next communication cycle. In this way, the user equipment may continue tracking a desired beam to maintain reliable data communications with a communication node.

Abstract: Frequency spectrum of wireless transmission signals are allocated based on availability and regulatory requirements. To ensure transmission signals are within designated channel boundary, user equipment utilizes processing circuitry coupled to a transceiver to pre-compensate for estimated frequency shift at the time of transmissions. Certain guard bands are provided such that the actual transmission signals with the frequency pre-compensation are within the designated channel boundary. Additionally, or alternatively, the user equipment utilizes the processing circuitry to pre-compensate for estimated time shift based on a crystal drift using temperature measurement.

Abstract: A method for determining a customized medication for weight-loss including a variable composition. The variable composition includes one or more additive ingredients selected from a plurality of additive ingredients. The method includes the steps of displaying a plurality of questions to a user, receiving user responses from the user corresponding to each question in the plurality of questions, analyzing the user responses, disqualifying any of the additive ingredients in the plurality of additive ingredients based on the user responses, and creating a customized medication for the user once a user response has been received for each of the questions in the plurality of questions. The customized medication includes any of the additive ingredients in the variable composition which have not been disqualified.

Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.

Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.

Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.

Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.

Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.

Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.