Patents by Inventor Nishkam Ravi

Nishkam Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9535826
    Abstract: There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: January 3, 2017
    Assignee: NEC Corporation
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar, Bin Ren
  • Patent number: 9201638
    Abstract: Various methods are provided directed to a compiler-guided software accelerator for iterative HADOOP® jobs. A method includes identifying intermediate data, generated by an iterative HADOOP® application, below a predetermined threshold size and used less than a predetermined threshold time period. The intermediate data is stored in a memory device. The method further includes minimizing input, output, and synchronization overhead for the intermediate data by selectively using at any given time any one of a Message Passing Interface and Distributed File System as a communication layer. The Message Passing Interface is co-located with the HADOOP® Distributed File System.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 1, 2015
    Assignee: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Abhishek Verma, Srimat T. Chakradhar
  • Patent number: 9038088
    Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 19, 2015
    Assignee: NEC Laboratories America, Inc.
    Inventors: Rajat Phull, Srihari Cadambi, Nishkam Ravi, Srimat Chakradhar
  • Patent number: 8997073
    Abstract: A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and accelerator memory, including adding relaxed semantics to a directive based language in the heterogenous computing for allowing a suggesting rather than specifying a parallel code region as an offloadable candidate, and identifying one or more offloadable tasks in a neighborhood of code region marked by the directive.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 31, 2015
    Assignee: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
  • Publication number: 20150067225
    Abstract: There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.
    Type: Application
    Filed: June 2, 2014
    Publication date: March 5, 2015
    Applicant: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar, Bin Ren
  • Patent number: 8918770
    Abstract: A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 23, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
  • Patent number: 8893103
    Abstract: Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a central processing unit (CPU) sub-part; executing the sampling sub-part with a processor to determine loop characteristics including memory- and processor-operations executed by the loop; identifying optimal split boundaries based on the loop characteristics such that the MIC sub-part will complete in a same amount of time when executed on a MIC processor as the CPU sub-part will take when executed on a CPU; and modifying the input source code to split the loop at the identified boundaries, such that the MIC sub-part is executed on a MIC processor and the CPU sub-part is concurrently executed on a CPU.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
  • Publication number: 20140325495
    Abstract: A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and accelerator memory, including adding relaxed semantics to a directive based language in the heterogenous computing for allowing a suggesting rather than specifying a parallel code region as an offloadable candidate, and identifying one or more offloadable tasks in a neighborhood of code region marked by the directive.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 30, 2014
    Applicant: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
  • Patent number: 8793674
    Abstract: A method for compiler-guided optimization of MapReduce type applications that includes applying transformations and optimizations to JAVA bytecode of an original application by an instrumenter which carries out static analysis to determine application properties depending on the optimization being performed and provides an output of optimized JAVA bytecode, and executing the application and analyzing generated trace and feeds information back into the instrumenter by a trace analyzer, the trace analyzer and instrumenter invoking each other iteratively and exchanging information through files.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: July 29, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Jun Liu, Srimat T. Chakradhar
  • Patent number: 8793675
    Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
  • Publication number: 20140053131
    Abstract: Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a central processing unit (CPU) sub-part; executing the sampling sub-part with a processor to determine loop characteristics including memory- and processor-operations executed by the loop; identifying optimal split boundaries based on the loop characteristics such that the MIC sub-part will complete in a same amount of time when executed on a MIC processor as the CPU sub-part will take when executed on a CPU; and modifying the input source code to split the loop at the identified boundaries, such that the MIC sub-part is executed on a MIC processor and the CPU sub-part is concurrently executed on a CPU.
    Type: Application
    Filed: July 12, 2013
    Publication date: February 20, 2014
    Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
  • Publication number: 20140047422
    Abstract: Various methods are provided directed to a compiler-guided software accelerator for iterative HADOOP jobs. A method includes identifying intermediate data, generated by an iterative HADOOP application, below a predetermined threshold size and used less than a predetermined threshold time period. The intermediate data is stored in a memory device. The method further includes minimizing input, output, and synchronization overhead for the intermediate data by selectively using at any given time any one of a Message Passing Interface and Distributed File System as a communication layer. The Message Passing Interface is co-located with the HADOOP Distributed File System.
    Type: Application
    Filed: June 21, 2013
    Publication date: February 13, 2014
    Inventors: Nishkam Ravi, Abhishek Verma, Srimat T. Chakradhar
  • Publication number: 20130097593
    Abstract: A method for compiler-guided optimization of MapReduce type applications that includes applying transformations and optimizations to Java bytecode of an original application by an instrumenter which carries out static analysis to determine application properties depending on the optimization being performed and provides an output of optimized Java bytecode, and executing the application and analyzing generated trace and feeds information back into the instrumenter by a trace analyzer, the trace analyzer and instrumenter invoking each other iteratively and exchanging information through files.
    Type: Application
    Filed: September 18, 2012
    Publication date: April 18, 2013
    Applicant: NEC Laboratories America, Inc.
    Inventors: Nishkam Ravi, Jun Liu, Srimat T. Chakradhar
  • Publication number: 20130055225
    Abstract: A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 28, 2013
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
  • Publication number: 20130055224
    Abstract: A system and method for compiling includes parsing code of an application stored in a computer readable storage medium to identify one or more parallelizable code portions. At least one parallelizable code portion is optimized by transforming offload construct code portions to provide an optimized application.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 28, 2013
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
  • Publication number: 20120233486
    Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 13, 2012
    Applicant: NEC Laboratories America, Inc.
    Inventors: Rajat Phull, Srihari Cadambi, Nishkam Ravi, Srimat Chakradhar
  • Publication number: 20120167069
    Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 28, 2012
    Inventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
  • Patent number: 7743422
    Abstract: A portable device for connecting to a host information processing platform includes: a digital information storage medium storing an operating system image, secure data, applications, and system state of an owner of the portable device, wherein the medium is in read only mode until a set of tests are run on the host platform; and a platform validation program for: running the plurality of tests on the host computer to determine whether the host is safe, depending on the outcome of the tests, presenting the owner with a user-identifiable message, prompting the owner to enter decryption credentials, and receiving the decryption credentials. The portable device could also optionally include subsystems that provide additional functionality to the owner such as media playback, communications, and entertainment.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: June 22, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekhar Narayanaswami, Mandayam Thondanur Raghunath, Nishkam Ravi, Marcel-Catalin Rosu
  • Publication number: 20080046990
    Abstract: A portable device for connecting to a host information processing platform includes: a digital information storage medium storing an operating system image, secure data, applications, and system state of an owner of the portable device, wherein the medium is in read only mode until a set of tests are run on the host platform; and a platform validation program for: running the plurality of tests on the host computer to determine whether the host is safe, depending on the outcome of the tests, presenting the owner with a user-identifiable message, prompting the owner to enter decryption credentials, and receiving the decryption credentials. The portable device could also optionally include subsystems that provide additional functionality to the owner such as media playback, communications, and entertainment.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Applicant: International Business Machines Corporation
    Inventors: Chandrasekhar Narayanaswami, Mandayam Thondanur Raghunath, Nishkam Ravi, Marcel-Catalin Rosu