Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Abstract: A computer implemented method and system for managing recruitment interactions provides a recruitment interaction management platform (RIMP) that acquires profile information associated with multiple roles from multiple users and recruitment advisory information from one or more of the users and/or first external sources via a network, for creating one or more candidate profiles for candidates. The RIMP matches the candidate profiles with a recruiting requirement acquired from one or more of the users or second external sources via the network, based on matching criteria to generate a candidate list that matches the recruiting requirement; dynamically assigns a rating to each of the users based on their roles, the profile information, an outcome of a transaction performed between recruiters and the candidates, and predetermined rating criteria associated with the roles; and allocates incentives to each of the users based on the roles, the assigned rating, and predetermined incentive allocation criteria.

Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit, which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.

Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.

Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.

Abstract: A carry save multiplier receives two input values having respective bit lengths A and B and provides sum and carry values, each having bit lengths A+B+1. A carry prediction circuit receives the most significant bit of the sum and carry values and provides an extension bit to be merged with less significant bits of the sum and carry bits. A carry save adder receives the altered sum and carry values, as well as a third input value to provide second sum and carry values. The second sum and carry values are added in a carry propagate adder to form a resulting value. This allows for a faster multiplication to form a product, and the faster addition of this product to another value such as an accumulator value.

Abstract: An adder tree is partitioned into two parts. One multiplexer provides a first bit group to the first part of the tree. A second multiplexer provides a second bit group to the second part of the tree. The two multiplexers provide the same bits groups to the respective parts in response to a first instruction, and provide different bit groups in response to a second instruction. Therefore, the first instruction allows for the single multiplication of the number represented by the first bit group by another number provided to collectively represented to both parts of the tree. The second instruction causes the multiplication of the first bit group by the third bit group in the first part of the adder tree, and causes another multiplication of the second bit group by the fourth bit group in the second part of the adder tree.

Abstract: An apparatus for high speed signal propagation across a net in an integrated circuit operates with a driver that is coupled to the net, for driving signals across the net. A first transition assist driver (TAD) is coupled to a first node in the net and is capable of pulling the voltage level of the first node in response to the voltage level of the first node reaching a threshold value. The threshold value can be adjusted in order to increase the switching speed or, alternatively, the noise immunity of the first TAD. A second TAD is coupled to a second node in the net and is capable of pulling the voltage level of the second node in response to the voltage level of the second node reaching the threshold value. The apparatus is used for increasing the propagation speed of signals that are transmitted in a microprocessor block or other stages in an integrated circuit.

Abstract: An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response to a carry enable instruction. The logic unit outputs a bit that is independent of the carry bit in response to a lack of a carry enable instruction.

Abstract: A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

Abstract: A multiplier is configured to multiply two signed values to generate sum and carry bit groups representing, in redundant form, a product of the first and second signed values. A sign determining circuit is configured generate a sign bit representing a sign of the product. An extension unit is configured to receive the sum most significant bit, the sign bit, and the carry most significant bit. The extension output terminal configured to carry a replacement bit and an extension bit, the replacement bit having a same weight as the sum most significant bit. The extension unit is structured such that the replacement bit has one binary state only if the sum most significant bit and the carry most significant bit are different. The extension unit is structured such that the extension bit has one binary state only if the sign bit is a binary zero and the sum most significant bit and the carry most significant bit are the same.