Patents by Inventor Nital Patwa
Nital Patwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170265801Abstract: A bruxism detection system is provided that includes a chin-mounted acceleration sensor for detection of teeth grinding and teeth tapping. The system generally includes an acceleration sensor that is adapted to be removably and externally mounted with respect to an individual's chin, a bruxism recording and processing system operable on a local processor, and bruxism analysis software that is operable on the local processor or an adjoint processor (or a combination thereof). The system is designed to be used in any convenient location, including an individual's home, and is generally reusable by multiple people, thus reducing the cost of bruxism diagnosis and bringing a reliable and effective diagnosis tool to the general public.Type: ApplicationFiled: March 15, 2017Publication date: September 21, 2017Inventors: Aalok Nital Patwa, Manasi Nital Patwa
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Patent number: 9684613Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.Type: GrantFiled: May 15, 2014Date of Patent: June 20, 2017Assignee: Seagate Technology LLCInventors: Nital Patwa, Timothy Canepa, Yimin Chen
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Publication number: 20140344492Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.Type: ApplicationFiled: May 15, 2014Publication date: November 20, 2014Applicant: LSI CorporationInventors: Nital Patwa, Timothy Canepa, Yimin Chen
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Publication number: 20140331001Abstract: Methods and systems may perform one or more operations for solid state device administrative command execution including, but not limited to: receiving, in at least one administrative command queue, at least one administrative command affecting at least one submission queue; halting enqueuing of one or more submission commands in the at least one submission queue in response to the receiving the at least one administrative command affecting the at least one submission queue; adding at least one barrier command to at least one submission queue affected by the at least one administrative command; processing one or more commands in the at least one submission queue until the at least one barrier command in the at least one submission queue is processed; and processing the at least one administrative command affecting the at least one submission queue in response to the processing of the at least one barrier command.Type: ApplicationFiled: May 2, 2014Publication date: November 6, 2014Applicant: LSI CorporationInventors: Yang Liu, Nital Patwa, Ming-Ju Lee, Yimin Chen, Changyou Xu, Tim Canepa
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Patent number: 8775687Abstract: A method for processing a read sub-command in a secondary storage controller is disclosed. The method includes receiving the read sub-command from a primary storage controller; retrieving data in response to the read sub-command; utilizing a write request to write the retrieved data directly to a memory accessible by a host device; issuing an additional request to the same memory after the write request; receiving an indication of completion of the additional request; and reporting a sub-completion status to the primary storage controller.Type: GrantFiled: June 13, 2013Date of Patent: July 8, 2014Assignee: LSI CorporationInventors: Yang Liu, Nital Patwa, Changyou Xu, Timothy Canepa, Chien Chen
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Publication number: 20050089238Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose. registers. The general purpose. registers store information used by at least two of the instructions.Type: ApplicationFiled: June 10, 2004Publication date: April 28, 2005Applicant: ATI Technologies, Inc.Inventors: Chad Fogg, Nital Patwa, Parin Dalal, Stephen Purcell, Korbin Dyke, Steve Hale
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Patent number: 6745318Abstract: An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.Type: GrantFiled: August 18, 1999Date of Patent: June 1, 2004Inventors: Sanjay Mansingh, Niteen Patkar, Korbin Van Dyke, Stephen Hale, Dee Tovey, Nital Patwa, Stephen C. Purcell
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Patent number: 6127842Abstract: In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.Type: GrantFiled: June 24, 1999Date of Patent: October 3, 2000Assignee: ATI International SRLInventors: Parin B. Dalal, Steve Hale, Stephen C. Purcell, Nital Patwa
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Patent number: 5883423Abstract: A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the device channel region, and a gate insulator separating the device gate and channel region. The first and second diffusion regions are electrically connected to a positive power supply, and the device gate is electrically connected to a negative power supply. The decoupling capacitor may be formed proximate a signal driver in the integrated circuit. The decoupling capacitor may be formed without additional, expensive semiconductor fabrication steps and operates to minimize noise in the circuit.Type: GrantFiled: February 23, 1996Date of Patent: March 16, 1999Assignee: National Semiconductor CorporationInventors: Nital Patwa, Jayne Brown-West
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Patent number: 5796976Abstract: Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.Type: GrantFiled: January 23, 1996Date of Patent: August 18, 1998Assignee: Digital Equipment CorporationInventors: Bhavin Shah, Era Nangia, Gilbert Wolrich, Nital Patwa
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Patent number: 5740398Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: April 14, 1998Assignee: Cyrix CorporationInventors: Marc A. Quattromani, Nital Patwa
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Patent number: 5689454Abstract: Circuitry and methodology for pulse capture employs S-R latch, precharge, and switch circuitries for quickly sensing and capturing a logic pulse from dynamic logic circuitry. The present invention while having general application to any dynamic logic circuitry has particular application to random access memory (RAM), content addressable memory (CAM), and adder circuitries.Type: GrantFiled: January 11, 1996Date of Patent: November 18, 1997Assignee: Cyrix CorporationInventor: Nital Patwa
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Patent number: 5471598Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.Type: GrantFiled: October 18, 1993Date of Patent: November 28, 1995Assignee: Cyrix CorporationInventors: Marc A. Quattromani, Raul A. Garibay, Jr., Nital Patwa, Mark W. Hervin
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Patent number: 5418973Abstract: A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard.Type: GrantFiled: June 22, 1992Date of Patent: May 23, 1995Assignee: Digital Equipment CorporationInventors: James P. Ellis, Era Nangia, Nital Patwa, Bhavin Shah, Gilbert M. Wolrich