Abstract: A machine learning (ML) based asset monitoring system that automatically determines damage mechanisms (DMs) and generates automatically updated visualizations of assets that include equipment and lines of a processing plant is disclosed. The asset monitoring system is communicatively coupled to the assets of the plant and continuously receives process parameters associated with the various processes and equipment in the plant. Corrosion loops (CLs) are identified and automatically demarcated by the asset monitoring system. DMs are predicted for each of the assets using a ML model based on the process parameters and the corrosion loops. The data regarding the DMs, CLs and the process parameters are used to obtain equipment risk rankings for the assets. Multi-dimensional visualizations of the assets that display the state of the plant assets in real-time are generated.

Abstract: A machine learning (ML) based asset monitoring system that automatically determines damage mechanisms (DMs) and generates automatically updated visualizations of assets that include equipment and lines of a processing plant is disclosed. The asset monitoring system is communicatively coupled to the assets of the plant and continuously receives process parameters associated with the various processes and equipment in the plant. Corrosion loops (CLs) are identified and automatically demarcated by the asset monitoring system. DMs are predicted for each of the assets using a ML model based on the process parameters and the corrosion loops. The data regarding the DMs, CLs and the process parameters are used to obtain equipment risk rankings for the assets. Multi-dimensional visualizations of the assets that display the state of the plant assets in real-time are generated.

Abstract: An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.

Abstract: An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.