Patents by Inventor Nitin B. Desai

Nitin B. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7594318
    Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: September 29, 2009
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
  • Patent number: 7286366
    Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: October 23, 2007
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
  • Patent number: 7025596
    Abstract: A method and apparatus form electrical connections between electronic circuits and conductive threads (102, 104, 106, 108) that are interwoven into textile material (130). Electronic circuits (128), such as semiconductor dies, are connected to a carrier (132) and electrical connections (136) are made to conductive connection areas (110, 112, 114, 116) on the carrier (132). Conductive stitching (202, 204, 206, 208) provides electrical contacts for both the conductive connection areas (110, 112, 114, 116) on the carrier (132) and the conductive threads (102, 104, 106, 108) that are interwoven into the textile material (130). Optionally, a thin, flexible substrate material (132) is perforated during the stitching process.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: April 11, 2006
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, Bonnie J. Bachman, Alan R. Beatty, Stephen O. Bozzone, Nitin B. Desai, Ronald J. Kelley, Rami C. Levy
  • Patent number: 6972382
    Abstract: A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: December 6, 2005
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, Nitin B. Desai