Abstract: Systems and methods for an adaptive audio interface. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory including program instructions stored thereon that, upon execution by the processor, cause the IHS to: classify an audio environment; adjust an audio output gain setting based upon the classification; as a user changes position with respect to the IHS, monitor a distance between the user and the IHS; and modify the adjusted audio output gain setting based upon the monitoring, such that the modification causes a constant sound pressure level to be maintained at the user's position.

Abstract: Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module. In addition, the compressed data can be stored to one or more memory chips. Moreover, a read request may be received, wherein stored data is retrieved from at least one of the one or more memory chips in response to the request. Additionally, a decompression of the stored data may be conducted to obtain decompressed data.

Abstract: Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.

Abstract: Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.

Abstract: The present invention provides for dynamic thermal management of integrated circuits, including memory modules, within a computer system. The thermal management methodology described herein closely couples software operation to hardware operation of the computer system, and allows each system to run at near optimum performance levels without exceeding specified maximum temperature thresholds. In order to achieve such results, the present invention relates physical characteristics of the integrated circuit with physical characteristics of the internal chassis environment, and translates this relationship into a maximum software performance setting. The system monitors and adjusts software performance such that the maximum performance setting is not exceeded.

Abstract: A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory controller is also adapted to generate a power weight value based on a command type from the command information. The memory controller increments a power count of the one of the plurality of memory device ranks by the power weight value generated. The memory controller then compares the power count of the one of the plurality of memory device ranks to a threshold value set for the one of the plurality of memory device ranks. If it is determined that the power count exceeds the threshold value, the memory controller is adapted to throttle the one of the plurality of memory device ranks.

Abstract: A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.