Patents by Inventor Nitin Gupta

Nitin Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210058766
    Abstract: A method for group device triggering for IoT devices includes receiving, from a requesting node, a device trigger request message. The method further includes determining that the device trigger request message requests group IoT device triggering. The method further includes, in response to determining that the device trigger request message requests group IoT device triggering, resolving an external group identifier in the device trigger request message to individual international mobile station identifiers (IMSIs) corresponding to target IoT devices of the device trigger request message. The method further includes signaling a downstream node to trigger the target IoT devices.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 25, 2021
    Inventors: Venkatesh Aravamudhan, Anup Shivarajapura, Nitin Gupta
  • Patent number: 10929899
    Abstract: Systems and methods are provided for dynamic pricing of application programming interface (API) services such as machine learning API services. For example, a computing platform of an API service provider is configured to receive a request for a machine learning API service from a client computing device, obtain a dataset from the client computing device, utilize a classification engine to classify one or more attributes of the dataset and to classify an expected level of performance of the machine learning API service applied to the dataset based on the one or more classified attributes of the dataset, dynamically determine a pricing for the machine learning API service based on the classified expected level of performance of the dataset, and present the determined pricing for the machine learning API service on the client computing device.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vijay Ekambaram, Nitin Gupta, Pankaj S. Dayama
  • Patent number: 10915475
    Abstract: Aspects of the disclosure provide for management of a flash translation layer (FTL) for a non-volatile memory (NVM) in a Solid State Drive (SSD). The methods and apparatus provide a logical to physical (L2P) table where a first portion of the table is used for mapping frequently accessed hot data to a first subdrive in the NVM. Additionally, a second portion of the L2P table is provided for mapping cold data less frequently accessed than the hot data to a second subdrive, where logical blocks for storing the cold data in the second subdrive are larger than logical blocks storing the hot data in the first subdrive. Separation of the L2P table into hot and cold subdrives reduces the L2P table size that is needed in RAM for logical to physical memory mapping, while at the same time provides lower write amplification and latencies, especially for large capacity SSDs.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rishabh Dubey, Saugata Das Purkayastha, Chaitanya Kavirayani, Sampath Raja Murthy, Nitin Gupta, Revanasiddaiah Prabhuswamy Mathada
  • Publication number: 20210034698
    Abstract: One embodiment provides a method, including: receiving, from a client, (i) a task of annotating information, (ii) a set of instructions for performing the task, and (iii) client annotations for a subset of the information within the task; assigning the subset to a plurality of annotators; obtaining (i) annotator annotations for the subset and (ii) a response time for providing the annotator annotation for each piece of information within the subset; identifying improvements to the set of instructions by (i) comparing the annotator annotations to the client annotations and (ii) identifying discrepancies made by the annotators in view of the response time; and generating a new set of instructions, wherein the generating comprises (i) identifying at least one feature of the information that distinguishes correctly annotated information from incorrectly annotated information and (ii) generating an instruction from the at least one feature.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Shashank Mujumdar, Nitin Gupta, Arvind Agarwal, Sameep Mehta
  • Patent number: 10911053
    Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Kapil Kumar Tyagi
  • Patent number: 10902023
    Abstract: A continuously updated database is enhanced with virtual dynamic representations of taxonomic groups of records stored in the database. Each record of the database contains a vertical field that identifies a unique entity associated with that record and a horizontal attribute upon which a business decision, related to the corresponding unique entity, may be based. A taxonomic group of database records are defined for each distinct value of the vertical field, and all records in a particular taxonomic group contain a most desirable value of the horizontal field associated with that group's corresponding vertical-field value. The system creates and maintains a virtual representative of each taxonomic group that is automatically updated as the database is updated.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Elvina Chong, Nitin Gupta, Ravi Kumar Reddy Kanamatareddy
  • Publication number: 20210021672
    Abstract: According to one aspect, the subject matter described herein includes a method for service-specific group message delivery to narrowband Internet of things (IoT) devices. The method includes operations performed by a network node including at least one processor. The operations include receiving, on a first interface, a request for service-specific group message delivery to narrowband IoT devices supporting a specified service. The operations further include generating, by the network node, a message for service-specific group message delivery for transmission on a second interface, the message including a NB-IoT service information parameter for identifying a narrowband IoT service provided by the narrowband IoT devices supporting the specified service. The operations further include transmitting, from the network node and on the second interface the message for service-specific group message delivery to narrowband IoT devices.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Anup Shivarajapura, Venkatesh Aravamudhan, Nitin Gupta
  • Patent number: 10885019
    Abstract: One embodiment provides a method, including: receiving a plurality of review comments from each of a plurality of reviewers tasked with reviewing a document; categorizing each of the plurality of review comments into one of a plurality of review topics; identifying a conflict between a first review comment provided by one of the plurality of reviewers and a second review comment provided by another of the plurality of reviewers, wherein the identifying a conflict comprises (i) identifying a sentiment of the first review comment and a sentiment of the second review comment and (ii) determining that the sentiment of the first review comment and the sentiment of the second review comment are different; and generating a question set comprising a plurality of questions based upon a conflict identified for a review comment of the corresponding reviewer, wherein the corresponding reviewer answering the generated question resolves the conflict.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nitin Gupta, Ankush Gupta, Vijay Ekambaram
  • Patent number: 10878860
    Abstract: A data storage system includes a memory including a plurality of memory cells; and an interface coupled to the memory and a host. The interface includes a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal. The interface further includes a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to apply an impedance or forego applying an impedance to the multi-level data signal based on a previous state and a current state of the multi-level data signal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian
  • Publication number: 20200401169
    Abstract: A method is for operating an electronic device formed by a low dropout regulator (LDO) having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node. The electronic device is turned on by turning on the LDO, removing a DC bias from the second conduction terminal of the transistor by opening a first switch that selectively couples the second conduction terminal of the transistor to a supply node through a first diode coupled transistor and by opening a second switch that selectively couples the second conduction terminal of the transistor to a ground node through a second diode coupled transistor, and turning on the transistor. The electronic device is turned off by turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the LDO.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Kapil Kumar TYAGI, Nitin GUPTA
  • Publication number: 20200389175
    Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
    Type: Application
    Filed: June 8, 2020
    Publication date: December 10, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin GUPTA, Sagnik MUKHERJEE
  • Patent number: 10861508
    Abstract: A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D0-D7, to either be non-inverted or inverted, to save power consumed in the memory device.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Shiv Mathur, Nitin Gupta, Ramakrishnan Subramanian
  • Patent number: 10862487
    Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Gupta, Nitin Jain
  • Publication number: 20200380367
    Abstract: A method, computer system, and a computer program product for generating deep learning model insights using provenance data is provided. Embodiments of the present invention may include collecting provenance data. Embodiments of the present invention may include generating model insights based on the collected provenance data. Embodiments of the present invention may include generating a training model based on the generated model insights. Embodiments of the present invention may include reducing the training model size. Embodiments of the present invention may include creating a final trained model.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Nitin Gupta, HIMANSHU GUPTA, Rajmohan Chandrahasan, Sameep Mehta, Pranay Kumar Lohia
  • Patent number: 10838901
    Abstract: An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Vijay Sukhlal Chinchole, Siva Raghu Ram Voleti, Nitin Gupta, Ramakrishnan Karungulam Subramanian, Shiv Harit Mathur, Yan Li, Vinayak Ashok Ghatawade
  • Patent number: 10840915
    Abstract: A method of quickly locking a locked loop includes generating an intermediate reference signal having an intermediate reference frequency between a desired output frequency and a reference frequency of a reference signal, and setting an output frequency of a controllable oscillator to the desired output frequency using a first locked loop having a first loop divider value. The first loop divider value is set such that the intermediate reference frequency multiplied by the first loop divider value is equal to the desired output frequency. The controllable oscillator is then coupled to a second locked loop when the first locked loop locks, with the second locked loop is being activated. The first locked loop is then deactivated.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: November 17, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 10831721
    Abstract: Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. The virtual storage arrays overcomes bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client in the near future. Virtual storage arrays determine the association between requested storage blocks and corresponding high-level data structure entities to predict additional high-level data structure entities that are likely to be accessed. From this, the virtual storage array identifies the additional storage blocks for prefetching.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: November 10, 2020
    Assignee: RIVERBED TECHNOLOGY, INC.
    Inventors: David Tze-Si Wu, Steven McCanne, Michael J. Demmer, Nitin Gupta
  • Publication number: 20200343869
    Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 29, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin GUPTA, Prashutosh GUPTA
  • Patent number: 10817276
    Abstract: Methods, systems, and computer readable media for machine type communications/Internet of things (MTC/IoT) device updating are described. One method for machine type communications (MTC) device software updating includes receiving, by a control plane network node including at least one processor and via non-Internet protocol data delivery (NIDD) or non-access stratum (NAS) messaging, hardware and software version information regarding an MTC device. The method includes identifying, by the control plane network node, that a software update is available for the MTC device. The method further includes, in response determining that a software update is available for the MTC device, transmitting, by the control plane network node and via NIDD or NAS messaging, the software update to the MTC device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 27, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Nitin Gupta, Venkatesh Aravamudhan, Raghuvamshi vasudev Singh Thakur
  • Publication number: 20200333864
    Abstract: Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Nitin GUPTA, Bhavin ODEDARA, Raghu VOLETI