Patents by Inventor Nitin Parekh

Nitin Parekh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140165061
    Abstract: A computer-implemented method of managing resources in a virtual machine environment can include determining a specification of provisioning success corresponding to each of a plurality of jobs in the virtual machine environment, forming a prioritized listing of the plurality of jobs and, responsive to the specification of provisioning success and the prioritized listing, providing a resource specification for each of the plurality of jobs. The providing can include determining a first prediction of resource needs corresponding to each of a first subset of the plurality of jobs and determining a second prediction of resource needs corresponding to a second subset of the plurality of jobs.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Daniel H. Greene, Maurice Chu, Haitham Hindi, Bryan T. Preas, Nitin Parekh
  • Patent number: 8656404
    Abstract: A computer-implemented method of managing resources in a virtual machine environment can include determining a specification of provisioning success corresponding to each of multiple jobs in the virtual machine environment, determining a prediction of resource needs corresponding to each of the jobs, and determining a resource specification corresponding to each of the jobs based on the specification of provisioning success and the prediction of resource needs.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: February 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Daniel H. Greene, Maurice Chu, Haitham Hindi, Bryan T. Preas, Nitin Parekh
  • Patent number: 8268169
    Abstract: The water treatment system and method incorporating the use of a hydrodynamic separator to remove most of the total suspended solids (TSS) in source water being treated to thereby lighten the load on membrane filtration in the water treatment system and lower energy costs.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 18, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Meng H. Lean, Joe Zuback, Nitin Parekh, Norine E. Chang, Huangpin Ben Hsieh, Kai Melde
  • Publication number: 20120152814
    Abstract: The water treatment system and method incorporating the use of a hydrodynamic separator to remove most of the total suspended solids (TSS) in source water being treated to thereby lighten the load on membrane filtration in the water treatment system and lower energy costs.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Meng H. Lean, Joe Zuback, Nitin Parekh, Norine E. Chang, Huangpin Ben Hsieh, Kai Melde
  • Patent number: 7949560
    Abstract: A system and method for providing print advertisements is presented. A target audience is assembled from characteristics about readers. Advertising content is targeted to the target audience. The characteristics of the target audience are analyzed against the advertising content to identify potential advertisers. At least one of the potential advertisers is selected. At least one print advertisement for the selected advertiser is included on the document.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: May 24, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eric Peeters, Richard H. Bruce, Ana Arias, Bo Begole, Ross Bringans, Celia Chow, Lawrence Lee, Lisa Fahey, Linda Jacobson, Marc Mosko, Susan (Susie) Mulhern, Nitin Parekh, David Weinerth
  • Patent number: 7884634
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 8, 2011
    Assignee: Verigy (Singapore) Pte, Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Patent number: 7872482
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 18, 2011
    Assignee: Verigy (Singapore) Pte. Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20100100877
    Abstract: A computer-implemented method of managing resources in a virtual machine environment can include determining a specification of provisioning success corresponding to each of multiple jobs in the virtual machine environment, determining a prediction of resource needs corresponding to each of the jobs, and determining a resource specification corresponding to each of the jobs based on the specification of provisioning success and the prediction of resource needs.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Daniel H. Greene, Maurice Chu, Haitham Hindi, Bryan T. Preas, Nitin Parekh
  • Publication number: 20090153165
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: January 15, 2009
    Publication date: June 18, 2009
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20080313036
    Abstract: A system and method for providing advertisements in online and hardcopy mediums is presented. Advertising content is targeted to a target audience. The characteristics of the target audience are analyzed against the advertising content to identify potential advertisers. At least one of the potential advertisers is selected. One or more advertisements for the selected advertiser is included on a document. The document is provided on at least one of online and hardcopy mediums.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 18, 2008
    Inventors: Marc Mosko, Richard H. Bruce, Nitin Parekh, James (Bo) M.A. Begole, Lisa Fahey, Eric Peeters
  • Publication number: 20080313035
    Abstract: A system and method for providing print advertisements is presented. A target audience is assembled from characteristics about readers. Advertising content is targeted to the target audience. The characteristics of the target audience are analyzed against the advertising content to identify potential advertisers. At least one of the potential advertisers is selected. At least one print advertisement for the selected advertiser is included on the document.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 18, 2008
    Inventors: Eric Peeters, Richard H. Bruce, Ana Arias, James (Bo) M.A. Begole, Ross Bringans, Celia Chow, Lawrence Lee, Lisa Fahey, Linda Jacobson, Marc Mosko, Susan (Susie) Mulhern, Nitin Parekh, David Weinerth
  • Publication number: 20080246500
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: September 19, 2007
    Publication date: October 9, 2008
    Inventors: Fu Chiung CHONG, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Patent number: 7382142
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 3, 2008
    Assignee: NanoNexus, Inc.
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Publication number: 20050275418
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 15, 2005
    Inventors: Fu Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank Swiatowiec, Zhaohui Shan
  • Patent number: 6665575
    Abstract: A universal recipe editor for editing of semiconductor-manufacturing recipes. The universal recipe editor can read recipes from a wide variety of semiconductor-manufacturing machines from different manufacturers using recipe distributed object model (R-DOM) files. An R-DOM file is generated for each kind of recipe-file format to locate process parameters within proprietary recipe-file formats. The sequence of parameters in the R-DOM file matches the sequence in the recipe data file so that parameter may be mapped from recipe data files for display and editing. ASCII or binary recipe file formats are mapped from the recipe data file using R-DOM objects. Revision and authorng information is kept in a recipe information file for each recipe.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: December 16, 2003
    Assignee: FabCentric, Inc.
    Inventors: Manoj Betawar, Vrunda Bhagwat, Dinesh Goradia, Manish Mehta, Nitin Parekh
  • Patent number: 6415193
    Abstract: A universal recipe editor is for off-line viewing and editing of semiconductor-manufacturing recipes. The universal recipe editor can read recipes from a wide variety of semiconductor-manufacturing machines from different manufacturers using recipe distributed object model (R-DOM) files. An R-DOM file is generated for each kind of recipe-file format to locate process parameters within proprietary recipe-file formats. The sequence of parameters in the R-DOM file matches the sequence in the recipe data file so that parameters may be mapped from recipe data files for display and editing. ASCII or binary recipe file formats are mapped from the recipe data file using R-DOM objects. Revision and authoring information is kept in a recipe information file for each recipe. Each line of the recipe data file can specify a different process parameter. Security or access rights for each parameter is added for each parameter by including security codes on each line in the R-DOM file.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: July 2, 2002
    Assignee: FabCentric, Inc.
    Inventors: Manoj Betawar, Vrunda Bhagwat, Dinesh Goradia, Manish Mehta, Nitin Parekh
  • Publication number: 20020055804
    Abstract: A universal recipe editor is for off-line viewing and editing of semiconductor-manufacturing recipes. The universal recipe editor can read recipes from a wide variety of semiconductor-manufacturing machines from different manufacturers using recipe distributed object model (R-DOM) files. An R-DOM file is generated for each kind of recipe-file format to locate process parameters within proprietary recipe-file formats. The sequence of parameters in the R-DOM file matches the sequence in the recipe data file so that parameters may be mapped from recipe data files for display and editing. ASCII or binary recipe file formats are mapped from the recipe data file using R-DOM objects. Revision and authoring information is kept in a recipe information file for each recipe. Each line of the recipe data file can specify a different process parameter. Security or access rights for each parameter is added for each parameter by including security codes on each line in the R-DOM file.
    Type: Application
    Filed: January 18, 2002
    Publication date: May 9, 2002
    Inventors: Manoj Betawar, Vrunda Bhagwat, Dinesh Goradia, Manish Mehta, Nitin Parekh
  • Patent number: 5556507
    Abstract: The present invention is a method for providing multifunctional, contactless, interconnect technology that can simultaneously fabricate four features on a silicon wafer within the same metallization level including a diffusion barrier layer, a trim element (fuse), a higher resistivity local interconnect/strap, and a lower resistivity global interconnect. The fabrication only requires two lithographic operations and one metal deposition. A first metal (a refractory metal) film having constant thickness is sputter deposited on the silicon wafer. In the preferred embodiment, the refractory metal is titanitun-tungsten. A second metal fihn may be sputter deposited on the first metal film. The first metal fihn has a higher resistivity than the second metal film. In the preferred embodiment, the second metal is aluminum-copper. Four features may be defined using a first mask. The features are etched and the first mask is removed. Three of the four features may be further defined using a second, non-critical mask.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: September 17, 1996
    Assignee: Silicon Systems, Inc.
    Inventors: Nitin Parekh, Dominic Massetti