Publication number: 20070063883
Abstract: A circuit is provided for receiving an analog signal and providing a digital signal. It includes pre-amplifiers (601, 603, 605, 607), where each pre-amplifier (601, 603, 605, 607) receives an analog signal (Vin) and a respective reference signal (REF1-REFn). Each of the pre-amplifiers (601, 603, 605, 607) produces an output signal responsive to the analog signal and the respective reference signal. For each of the pre-amplifiers (601, 603, 605, 607), there is provided two or more latches (615, 617, 619, 621, 623, 625) corresponding thereto. Each of the latches (615, 617, 619, 621, 623, 625) receives the output signal and a clock signal and produces a respective digital signal responsive thereto, the clock signal being interleaved. For each of the pre-amplifiers (601, 603, 605, 607), there is a multiplexer (627, 629, 631) corresponding thereto. The multiplexer (627, 629, 631) multiplexes between the respective digital signals to produce a bit in a digital signal.
Type:
Application
Filed:
September 20, 2005
Publication date:
March 22, 2007
Inventors:
Phuong Huynh, Nitin Sharma