Patents by Inventor Nitya Ranganathan

Nitya Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multimode prefetcher
    Patent number: 9026739
    Abstract: One or more lines of a cache are prefetched according to a first prefetch routine while training a prefetcher to prefetch one or more lines of the cache according to a second prefetch routine. In response to determining that the prefetcher has been trained, one or more lines of the cache may be prefetched according to the second prefetch routine.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srilatha Manne, Nitya Ranganathan, Paul Keltcher, Donald W. McCauley
  • MULTIMODE PREFETCHER
    Publication number: 20130238861
    Abstract: One or more lines of a cache are prefetched according to a first prefetch routine while training a prefetcher to prefetch one or more lines of the cache according to a second prefetch routine. In response to determining that the prefetcher has been trained, one or more lines of the cache may be prefetched according to the second prefetch routine.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Inventors: Srilatha Manne, Nitya Ranganathan, Paul Keltcher, Donald W. McCauley
  • Dynamically composing processor cores to form logical processors
    Patent number: 8180997
    Abstract: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 15, 2012
    Assignee: Board of Regents, University of Texas System
    Inventors: Douglas C. Burger, Stephen W. Keckler, Robert McDonald, Paul Gratz, Nitya Ranganathan, Lakshminarasimhan Sethumadhavan, Karthikevan Sankaralingam, Ramadass Nagarajan, Changkyu Kim, Haiming Liu
  • Control-flow prediction using multiple independent predictors
    Patent number: 8127119
    Abstract: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: February 28, 2012
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Doug Burger, Stephen W. Keckler, Nitya Ranganathan
  • Control-Flow Prediction Using Multiple Independent Predictors
    Publication number: 20100146249
    Abstract: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Applicant: Intellectual Ventures Management, LLC
    Inventors: Doug Burger, Stephen W. Keckler, Nitya Ranganathan
  • DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS
    Publication number: 20090013160
    Abstract: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 8, 2009
    Applicant: Board of Regents, The University of Texas System
    Inventors: Douglas C. Burger, Stephen W. Keckler, Robert McDonald, Paul Gratz, Nitya Ranganathan, Lakshminarasimhan Sethumadhavan, Karthikevan Sankaralingam, Ramadass Nagarajan, Changkyu Kim, Haiming Liu