Patents by Inventor Noam Abda

Noam Abda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present
    Patent number: 8499139
    Abstract: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: July 30, 2013
    Assignee: LSI Corporation
    Inventors: Leonid Dubrovin, Alexander Rabinovitch, Hagit Margolin, Noam Abda
  • SPECULATIVE MEMORY WRITE IN A PIPELINED PROCESSOR
    Publication number: 20130046961
    Abstract: An apparatus generally having an interface circuit and a processor. The interface circuit may have a queue and a connection to a memory. The processor may have a pipeline. The processor is generally configured to (i) place an address in the queue in response to processing a first instruction in a first stage of the pipeline, (ii) generate a flag by processing a second instruction in a second stage of the pipeline, the second instruction may be processed in the second stage after the first instruction is processed in the first stage, and (iii) generate a signal based on the flag in a third stage of the pipeline. The third stage may be situated in the pipeline after the second stage. The interface circuit is generally configured to cancel the address from the queue without transferring the address to the memory in response to the signal having a disabled value.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Inventors: Alexander Rabinovitch, Leonid Dubrovin, Eran Dosh, Noam Abda, Vered Antebi
  • ELIMINATION OF READ-AFTER-WRITE RESOURCE CONFLICTS IN A PIPELINE OF A PROCESSOR
    Publication number: 20120042152
    Abstract: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Inventors: Leonid Dubrovin, Alexander Rabinovitch, Hagit Margolin, Noam Abda