Patents by Inventor Noboru Asahi

Noboru Asahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10181460
    Abstract: A method for manufacturing a semiconductor device includes laminating a plurality of semiconductor wafers via an adhesive, heating such that the adhesive reaches a specific viscosity, and pressing the semiconductor wafers under a provisional pressure bonding load such that a gap between solder of through-electrodes provided to chip parts and through-electrodes of an adjacent semiconductor wafer falls within a specific range that is greater than zero, to produce a provisional pressure-bonded laminate; cutting the provisional pressure-bonded laminate with a cutter to produce a provisional pressure-bonded laminate chip part; and heating the provisional pressure-bonded laminate chip part to at least curing temperature of the adhesive and at least melting point of the solder, and pressing the provisional pressure-bonded laminate chip part under a main pressure bonding load to produce a main pressure-bonded laminate chip part such that the solder comes into contact with the through-electrodes of adjacent chip parts
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 15, 2019
    Assignee: TORAY ENGINEERING CO., LTD.
    Inventors: Noboru Asahi, Yoshiyuki Arai, Yoshinori Miyamoto, Shimpei Aoki, Masatsugu Nimura
  • Publication number: 20180096980
    Abstract: A method for manufacturing a semiconductor device includes laminating a plurality of semiconductor wafers via an adhesive, heating such that the adhesive reaches a specific viscosity, and pressing the semiconductor wafers under a provisional pressure bonding load such that a gap between solder of through-electrodes provided to chip parts and through-electrodes of an adjacent semiconductor wafer falls within a specific range that is greater than zero, to produce a provisional pressure-bonded laminate; cutting the provisional pressure-bonded laminate with a cutter to produce a provisional pressure-bonded laminate chip part; and heating the provisional pressure-bonded laminate chip part to at least curing temperature of the adhesive and at least melting point of the solder, and pressing the provisional pressure-bonded laminate chip part under a main pressure bonding load to produce a main pressure-bonded laminate chip part such that the solder comes into contact with the through-electrodes of adjacent chip parts
    Type: Application
    Filed: March 29, 2016
    Publication date: April 5, 2018
    Inventors: Noboru ASAHI, Yoshiyuki ARAI, Yoshinori MIYAMOTO, Shimpei AOKI, Masatsugu NIMURA
  • Publication number: 20150050778
    Abstract: Disclosed is a method for producing a semiconductor device in which solder joints are made between a semiconductor chip with bumps and a substrate with electrodes corresponding to the bumps through a thermosetting adhesive layer, the method including the successive steps of: (A) forming a thermosetting adhesive layer in advance on a surface including bumps of the semiconductor chip; (B) laying a surface on the thermosetting adhesive layer side of the semiconductor chip, on which the thermosetting adhesive layer is formed, and a substrate one upon another, followed by pre-bonding using a heat tool to obtain a pre-bonded laminate; and (C) interposing a protective film having a thermal conductivity of 100 W/mK or more between the heat tool and a surface on the semiconductor chip side of the pre-bonded laminate, melting a solder between the semiconductor chips and the substrate and simultaneously curing the thermosetting adhesive layer using the heat tool.
    Type: Application
    Filed: February 20, 2013
    Publication date: February 19, 2015
    Inventors: Noboru Asahi, Toshihisa Nonaka, Shoichi Niizeki
  • Patent number: 7444058
    Abstract: This invention is a resin composition for optical wiring, comprising an inorganic filler with an average particle size of 1 nm to 100 nm and a resin, having a ratio nf/nr (where nf is the refractive index of the inorganic filler and nr is the refractive index of the resin) of 0.8 to 1.2, a thermal expansion coefficient of ?1×10?5 /° C. to 4×10?5/° C., and a true dependency value of its refractive index on the temperature of ?1×10?4/° C. to 1×10?4/° C. in a temperature range from ?20° C. to 90° C., and substantially incapable of absorbing light in a wavelength range from 0.6 to 0.9 ?m or from 1.2 to 1.6 ?m. This invention also provides an optoelectronic circuit board.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: October 28, 2008
    Assignee: Toray Industries, Inc.
    Inventors: Toshihisa Nonaka, Noboru Asahi, Yoshiko Tatsuta
  • Publication number: 20070147767
    Abstract: This invention is a resin composition for optical wiring, comprising an inorganic filler with an average particle size of 1 nm to 100 nm and a resin, having a ratio nf/nr (where nf is the refractive index of the inorganic filler and nr is the refractive index of the resin) of 0.8 to 1.2, a thermal expansion coefficient of ?1×10?5/° C. to 4×105/° C., and a true dependency value of its refractive index on the temperature of ?1×10?4/° C. to 1×10?4/° C. in a temperature range from ?20° C. to 90° C., and substantially incapable of absorbing light in a wavelength range from 0.6 to 0.9 ?m or from 1.2 to 1.6 ?m. This invention also provides an optoelectronic circuit board.
    Type: Application
    Filed: March 5, 2007
    Publication date: June 28, 2007
    Inventors: Toshihisa Nonaka, Noboru Asahi, Yoshiko Tatsuta