Abstract: A door opening and closing mechanism includes: a door configured to open and close a front side opening of a housing, wherein an electronic device is housed in the housing and is exposed through the front side opening; and an accommodation mechanism configured to accommodate the door in the housing when the door is in open state. The accommodation mechanism includes: an opening and closing action unit configured to cause an opening action and a closing action of the door; and a retracting action unit configured to retract the opening and closing action unit into the housing so as to accommodate the door in the housing, when the door is brought in open state by the opening and closing action unit.

Abstract: A door opening and closing mechanism includes: a door configured to open and close a front side opening of a housing, wherein an electronic device is housed in the housing and is exposed through the front side opening; and an accommodation mechanism configured to accommodate the door in the housing when the door is in open state. The accommodation mechanism includes: an opening and closing action unit configured to cause an opening action and a closing action of the door; and a retracting action unit configured to retract the opening and closing action unit into the housing so as to accommodate the door in the housing, when the door is brought in open state by the opening and closing action unit.

Abstract: [Object] Object of the present invention is to improve accuracy of the travelling test of a tested vehicle on a chassis dynamometer, and to increase realistic feeling of the travelling test. [Means to solve] A driver's aid device 5 displays, on a main screen 11, a travelling speed pattern 12 that is a driving pattern for performing a performance evaluation test of a tested vehicle 6. The main screen 11 displays thereon topographical feature information 13 of a road where the travelling test is carried out. A marker 14 that indicates a vehicle state is shown at an intersection of the topographical feature information 13 and a reference line 15 that indicates a present position of the tested vehicle 6. This marker 14 is shown with the marker 14 inclined in accordance with a gradient of the road where the test is carried out. Further, a curve band 28 indicating curve information of the road where the travelling test is carried out is shown on the main screen 11.

Abstract: [Object] Object of the present invention is to improve accuracy of the travelling test of a tested vehicle on a chassis dynamometer, and to increase realistic feeling of the travelling test. [Means to solve] A driver's aid device 5 displays, on a main screen 11, a travelling speed pattern 12 that is a driving pattern for performing a performance evaluation test of a tested vehicle 6. The main screen 11 displays thereon topographical feature information 13 of a road where the travelling test is carried out. A marker 14 that indicates a vehicle state is shown at an intersection of the topographical feature information 13 and a reference line 15 that indicates a present position of the tested vehicle 6. This marker 14 is shown with the marker 14 inclined in accordance with a gradient of the road where the test is carried out. Further, a curve band 28 indicating curve information of the road where the travelling test is carried out is shown on the main screen 11.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: A unitary semiconductor integrated circuit is constructed using a non-threshold logic NTL circuit for a circuit which has a light load or a light load driving capability, using an NTL circuit additionally provided with an emitter-follower output circuit for effecting a circuit having a comparatively heavy load, and using a super pull-down logic (SPL) circuit for effecting a circuit having a heavy load. The NTL circuit thereof which receives an output signal generated by the emitter-follower output circuit or from the SPL circuit associated with a preceding logic gate circuit stage uses, as its operating voltage, the operating voltage of the emitter-follower output circuit or that of the SPL circuit.

Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.