Abstract: By a state estimation device or a state estimation method, image data is read, a feature point included in the image data is extracted, the feature point is tracked, a position, a velocity, or an attitude of a mobile object is calculated based on inertia data, a bias error of an inertial measurement unit is calculated, correction data is calculated by removing the bias error from the inertia data, and a state including at least one of the position, the velocity, or the attitude of the mobile object is estimated based on the correction data.

Abstract: An obstacle detection apparatus that detects an obstacle existing around a vehicle is provided to include an ultrasonic sensor and a controller. The ultrasonic sensor is provided in the vehicle at a position having a predetermined height from a road surface. The ultrasonic sensor includes a plurality of ultrasonic elements configured to transmit an exploration wave toward outside of the vehicle, and receive a reflected wave reflected by an obstacle as a reception wave. The controller is configured to derive (i) an obstacle distance and (ii) an obstacle height based on an intensity of the reception wave received by each of the plurality of ultrasonic elements and a phase difference in the reception wave received by each of the plurality of ultrasonic elements.

Abstract: A gyroscope includes a MEMS sensor having a drive signal input terminal, a drive signal output terminal, and a sense signal output terminal. The gyroscope further includes a quadrature demodulator that demodulates a modulated sense signal and offset canceller circuits that cancel a direct current offset component included in an in-phase signal and a quadrature signal of the sense signal. The gyroscope has a quadrature error detector that detects a quadrature error based on the signals input from the offset canceller circuits and outputs an error signal. The gyroscope also has an IQ corrector circuit that receives the in-phase signal and the quadrature signal of the sense signal as inputs, and outputs a phase signal with a phase based on the error signal.

Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Abstract: A vibration type gyroscope uses a resonator formed of a MEMS. At the time of startup, a lock state determination unit stabilizes an amplitude of a drive signal and outputs a lock signal when the amplitude is stabilized. A phase shifter generates an orthogonal signal by shifting, by 90°, the phase of the drive signal, and a phase compensator outputs a phase signal having a phase corresponding to a control signal based on the orthogonal signal and the in-phase signal of the drive signal. A multiplier multiplies a sense signal and the phase signal outputted from the phase compensator, and a control LPF performs filtering on a multiplication result. A control unit inputs a zero level signal to a PI controller during an initial state, and starts phase control by receiving an output signal of the control LPF, and ends the control when the signal is stabilized around the zero level.

Abstract: A vibration type gyroscope uses a resonator formed of a MEMS. At the time of startup, a lock state determination unit stabilizes an amplitude of a drive signal and outputs a lock signal when the amplitude is stabilized. A phase shifter generates an orthogonal signal by shifting, by 90°, the phase of the drive signal, and a phase compensator outputs a phase signal having a phase corresponding to a control signal based on the orthogonal signal and the in-phase signal of the drive signal. A multiplier multiplies a sense signal and the phase signal outputted from the phase compensator, and a control LPF performs filtering on a multiplication result. A control unit inputs a zero level signal to a PI controller during an initial state, and starts phase control by receiving an output signal of the control LPF, and ends the control when the signal is stabilized around the zero level.

Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Abstract: A gyroscope includes a MEMS sensor having a drive signal input terminal, a drive signal output terminal, and a sense signal output terminal. The gyroscope further includes a quadrature demodulator that demodulates a modulated sense signal and offset canceller circuits that cancel a direct current offset component included in an in-phase signal and a quadrature signal of the sense signal. The gyroscope has a quadrature error detector that detects a quadrature error based on the signals input from the offset canceller circuits and outputs an error signal. The gyroscope also has an IQ corrector circuit that receives the in-phase signal and the quadrature signal of the sense signal as inputs, and outputs a phase signal with a phase based on the error signal.

Abstract: A communication system includes a transmission path and multiple nodes. At least one of the multiple nodes includes a second communication portion and a control portion in addition to a first communication portion. When the control portion performs a high speed communication, the control portion shifts the first communication portion included in each of the remaining multiple nodes to a sleep mode. The second communication portion performs a differential communication at a higher speed than the first communication portion using a differential signal. In the differential signal, a maximum of a potential difference between the pair of communication lines is equal to or less than a recessive threshold value, and a minimum of the potential difference between the pair of communication lines is a negative voltage value that has a polarity opposite to the recessive threshold value of the first communication portion.

Abstract: A communication system includes a transmission path and multiple nodes. At least one of the multiple nodes includes a second communication portion and a control portion in addition to a first communication portion. When the control portion performs a high speed communication, the control portion shifts the first communication portion included in each of the remaining multiple nodes to a sleep mode. The second communication portion performs a differential communication at a higher speed than the first communication portion using a differential signal. In the differential signal, a maximum of a potential difference between the pair of communication lines is equal to or less than a recessive threshold value, and a minimum of the potential difference between the pair of communication lines is a negative voltage value that has a polarity opposite to the recessive threshold value of the first communication portion.

Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Abstract: A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

Abstract: A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

Abstract: A communication system includes multiple communication nodes and a communication line. The multiple communication nodes include a master and multiple slaves. The communication line cascade-connects the communication nodes and supplies electricity. The communication line corresponds to a feeder line. Each of the communication nodes is connected with the communication line through an inductor to be supplied with electricity. The each of the communication nodes is AC coupled to the communication line to transmit and receive a communication signal. The master and the slaves perform a bidirectional communication. A communication slave is provided. The communication slave is connected with a communication line through an inductor to be supplied with electricity. A communication master is provided.

Abstract: A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation.

Abstract: A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation.

Abstract: In a decision feedback equalizer, at least one of weighting devices that has a tap coefficient an absolute value of which is relatively larger than absolute values of tap coefficients of other weighting devices is referred to as a main weighting device, and delay elements are disposed asymmetrically on signal processing paths or updating paths of the tap coefficients of the weighting devices in such a manner that an updating interval of the tap coefficient of the main weighting device is shorter than updating intervals of the tap coefficients of the other weighting devices.

Abstract: In a decision feedback equalizer, at least one of weighting devices that has a tap coefficient an absolute value of which is relatively larger than absolute values of tap coefficients of other weighting devices is referred to as a main weighting device, and delay elements are disposed asymmetrically on signal processing paths or updating paths of the to coefficients of the weighting devices in such a manner that an updating interval of the tap coefficient of the main weighting device is shorter than updating intervals of the tap coefficients of the other weighting devices.

Abstract: A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).