Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit and is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion so as to protrude from the lamination surface with a height equal to or larger than that of the protruding connection portion.

Abstract: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.

Abstract: In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.

Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

Abstract: When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

Abstract: A neural network element, outputting an output signal in response to a plurality of input signals, comprises a history memory for accumulating and storing the plurality of input signals in a temporal order as history values. It also includes an output module for outputting the output signal when an internal state exceeds a predetermined threshold value, the internal state being based on a sum of the product of a plurality of input signals and corresponding coupling coefficients. The history values depend on change of the internal state. The neural network element is configured to subtract a predetermined value from the internal state immediately after the output module fires and performs learning for reinforcing or attenuating the coupling coefficient according to the history values after the output module fires.

Abstract: When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.

Abstract: Adhesive injection apparatus, designed to inject an adhesive into gaps between a plurality of layers of flat plate members, includes: a receptacle for holding therein the flat plate members; an evacuation section for evacuating the interior of the receptacle and the gaps between the flat plate members; an adhesive supply section for supplying the adhesive into the receptacle; and a gas introduction section for introducing a gas into the receptacle to produce a pressure difference between the interior of the receptacle and the gaps between the flat plate members, so as to allow the adhesive to be injected from all around the flat plate members into the gaps.

Abstract: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.

Abstract: A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit and is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion so as to protrude from the lamination surface with a height equal to or larger than that of the protruding connection portion.

Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.