Abstract: A microcomputer includes a CPU and a DRAM controller which is electrically connected to the CPU. The DRAM controller is also electrically connected to a DRAM for controlling the DRAM to execute dispersion CBR refresh operations in the normal mode. When the microcomputer is in a stand-by state, the DRAM controller so controls CAS and RAS control terminals of the DRAM as to have the DRAM enter into a CBR self-refresh mode. When the microcomputer receives an external bus hold demand during the stand-by state, the DRAM controller places the CAS and RAS control terminals of the DRAM into a high impedance state. When an external bus hold is released, the DRAM controller places the CAS and RAS control terminals of the DRAM into an inactive level to release at once the DRAM from the self-refresh mode and then place the DRAM into the self-refresh mode again.