Patents by Inventor Nobuaki Yamanaka
Nobuaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10677585Abstract: An occurrence of a noise in a light receiver is suppressed, and an accuracy of measuring a film thickness is improved. A film thickness measuring apparatus includes: a stage being in contact with only an end portion of a substrate; a reflection suppressing unit located separately from the stage in a region surrounded by the stage; a light source; and a light receiver which a first light made up of light, which has been emitted from the light source, reflected on an upper surface of the measured film and a second light reflected on an upper surface of the substrate enter. The reflection suppressing unit is located separately from a lower surface of the substrate exposed to atmosphere, and suppresses a reflection of light, which enters the reflection suppressing unit from the light source, to the light receiver.Type: GrantFiled: February 4, 2019Date of Patent: June 9, 2020Assignee: Mitsubishi Electric CorporationInventors: Yuichi Masumoto, Toru Jokaku, Nobuaki Yamanaka, Yosuke Nakanishi
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Publication number: 20190310074Abstract: An occurrence of a noise in a light receiver is suppressed, and an accuracy of measuring a film thickness is improved. A film thickness measuring apparatus includes: a stage being in contact with only an end portion of a substrate; a reflection suppressing unit located separately from the stage in a region surrounded by the stage; a light source; and a light receiver which a first light made up of light, which has been emitted from the light source, reflected on an upper surface of the measured film and a second light reflected on an upper surface of the substrate enter. The reflection suppressing unit is located separately from a lower surface of the substrate exposed to atmosphere, and suppresses a reflection of light, which enters the reflection suppressing unit from the light source, to the light receiver.Type: ApplicationFiled: February 4, 2019Publication date: October 10, 2019Applicant: Mitsubishi Electric CorporationInventors: Yuichi MASUMOTO, Toru JOKAKU, Nobuaki YAMANAKA, Yosuke NAKANISHI
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Patent number: 10242876Abstract: Provided is a method including the following steps: forming an insulating film having a thickness of 0.5 ?m or greater on an epitaxial layer provided with a well region, a source region, and a contact region, each being an impurity diffusion region; forming, in the insulating film, an opening that has a dimension of 2 mm×2 mm or greater in a plan view to expose at least part of the impurity diffusion region from the insulating film. The step of forming the opening in the insulating film is performed by the following separate steps: removing the insulating film so as to leave one-half or less of the thickness of the insulating film unremoved, through dry etching by the use of a photoresist; and removing the insulating film until the opening reaches the upper surface of the epitaxial layer, through wet etching by the use of the same photoresist.Type: GrantFiled: March 26, 2015Date of Patent: March 26, 2019Assignee: Mitsubishi Electric CorporationInventors: Daisuke Chikamori, Nobuaki Yamanaka, Takamichi Iwakawa
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Patent number: 10211056Abstract: A resist layer is applied to a metal film disposed on a semiconductor substrate, using a positive photoresist having photosensitivity to at least one wavelength. The resist layer is exposed to light including a region of the one wavelength. The exposed resist layer is developed. After the step of developing the resist layer, the metal film is subjected to wet etching with the resist layer used as a mask, in an etching apparatus. The etching apparatus is placed in an environment irradiated with a lighting apparatus that emits light with a wavelength equal to or shorter than the one wavelength cut off.Type: GrantFiled: April 25, 2014Date of Patent: February 19, 2019Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Yamanaka, Daisuke Chikamori, Yoshio Muto
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Patent number: 10074578Abstract: Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a method for producing the semiconductor device. The semiconductor device according to an aspect of the present invention includes at least one evaluation element disposed on a SiC wafer. The evaluation element includes a doped region doped with a dopant on the SiC wafer, and an insulating film partially covering the doped region. The insulating film includes a plurality of partial insulating films. The doped region includes a plurality of regions sectioned by the plurality of partial insulating films in a plan view.Type: GrantFiled: February 8, 2017Date of Patent: September 11, 2018Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Yamanaka, Daisuke Chikamori, Toru Jokaku
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Patent number: 9881818Abstract: A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.Type: GrantFiled: September 19, 2014Date of Patent: January 30, 2018Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Yamanaka, Daisuke Chikamori, Shinichirou Katsuki
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Publication number: 20180019130Abstract: Provided is a method including the following steps: forming an insulating film having a thickness of 0.5 ?m or greater on an epitaxial layer provided with a well region, a source region, and a contact region, each being an impurity diffusion region; forming, in the insulating film, an opening that has a dimension of 2 mm×2 mm or greater in a plan view to expose at least part of the impurity diffusion region from the insulating film. The step of forming the opening in the insulating film is performed by the following separate steps: removing the insulating film so as to leave one-half or less of the thickness of the insulating film unremoved, through dry etching by the use of a photoresist; and removing the insulating film until the opening reaches the upper surface of the epitaxial layer, through wet etching by the use of the same photoresist.Type: ApplicationFiled: March 26, 2015Publication date: January 18, 2018Applicant: Mitsubishi Electric CorporationInventors: Daisuke CHIKAMORI, Nobuaki YAMANAKA, Takamichi IWAKAWA
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Publication number: 20170352600Abstract: Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a method for producing the semiconductor device. The semiconductor device according to an aspect of the present invention includes at least one evaluation element disposed on a SiC wafer. The evaluation element includes a doped region doped with a dopant on the SiC wafer, and an insulating film partially covering the doped region. The insulating film includes a plurality of partial insulating films. The doped region includes a plurality of regions sectioned by the plurality of partial insulating films in a plan view.Type: ApplicationFiled: February 8, 2017Publication date: December 7, 2017Applicant: Mitsubishi Electric CorporationInventors: Nobuaki YAMANAKA, Daisuke CHIKAMORI, Toru JOKAKU
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Publication number: 20170154798Abstract: A method for manufacturing a semiconductor device, includes: a preparation step, a flow step, and a processing step. The preparation step prepares an etching solution by dissolving titanium in an ammonia-hydrogen peroxide solution in advance before use of the ammonia-hydrogen peroxide solution for etching. The flow step flows the etching solution after the preparation step so that a concentration of the etching solution in a processing bath is constant. The processing step etches a metal film on a semiconductor wafer with the etching solution by putting in the processing bath the semiconductor wafer having a resist film and the metal film after the flow step is started. The metal film is preferably formed of titanium, and a temperature of the etching solution is preferably adjusted by flowing the etching solution so that the etching solution flows via a temperature controller.Type: ApplicationFiled: September 19, 2014Publication date: June 1, 2017Applicant: Mitsubishi Electric CorporationInventors: Nobuaki YAMANAKA, Daisuke CHIKAMORI, Shinichirou KATSUKI
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Publication number: 20160351396Abstract: A resist layer is applied to a metal film disposed on a semiconductor substrate, using a positive photoresist having photosensitivity to at least one wavelength. The resist layer is exposed to light including a region of the one wavelength. The exposed resist layer is developed. After the step of developing the resist layer, the metal film is subjected to wet etching with the resist layer used as a mask, in an etching apparatus. The etching apparatus is placed in an environment irradiated with a lighting apparatus that emits light with a wavelength equal to or shorter than the one wavelength cut off.Type: ApplicationFiled: April 25, 2014Publication date: December 1, 2016Applicant: Mitsubishi Electric CorporationInventors: Nobuaki YAMANAKA, Daisuke CHIKAMORI, Yoshio MUTO
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Patent number: 6346482Abstract: There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.Type: GrantFiled: October 21, 1998Date of Patent: February 12, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Junko Matsumoto, Shigenori Sakamori, Akemi Teratani, Yoshihiro Kusumi, Tetsuhiro Fukao, Kazuyuki Ohmi, Kanji Tabaru, Nobuaki Yamanaka
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Publication number: 20010041450Abstract: There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.Type: ApplicationFiled: October 21, 1998Publication date: November 15, 2001Inventors: JUNKO MATSUMOTO, SHIGENORI SAKAMORI, AKEMI TERATANI, YOSHIHIRO KUSUMI, TETSUHIRO FUKAO, KAZUYUKI OHMI, KENJI TABARU, NOBUAKI YAMANAKA