Abstract: A pore device is used with a measurement device. The pore device includes a pore chip and a chip case which has a chamber partitioned by the pore chip. A measurement terminal group is provided to apply an electric signal from the measurement device to the chamber and output an electric signal generated in the chamber to the measurement device. Interface means is connected to a nonvolatile memory such that the nonvolatile memory is accessible from an outside of the pore device.

Abstract: A nanopore device includes a pore and an electrode pair. A current measurement unit applies a bias voltage that corresponds to a voltage setting command across an electrode pair and generates digital current data that corresponds to a current signal that flows through the nanopore device. A data processing apparatus generates the voltage setting command, acquires the current data and voltage data including information with respect to the waveform of the bias voltage Vb in a form in which they are associated on the time axis, and judges the kind of particles stored in the nanopore device based on the current data and the voltage data.

Abstract: A nanopore device measures a current signal Is that flows through the nanopore device, which has an aperture and an electrode pair. A transimpedance amplifier converts the current signal Is into a voltage signal Vs. A voltage source is configured to apply a DC bias voltage Vb across the electrode pair in a normal measurement mode, and to apply a calibration voltage Vcal across the electrode pair in a calibration mode. In the calibration mode, at least one circuit constant of a measurement apparatus is calibrated based on the output signal Vs of the transimpedance amplifier and the calibration voltage Vcal.

Abstract: A nanopore device measures a current signal Is that flows through the nanopore device, which has an aperture and an electrode pair. A transimpedance amplifier converts the current signal Is into a voltage signal Vs. A voltage source is configured to apply a DC bias voltage Vb across the electrode pair in a normal measurement mode, and to apply a calibration voltage Vcal across the electrode pair in a calibration mode. In the calibration mode, at least one circuit constant of a measurement apparatus is calibrated based on the output signal Vs of the transimpedance amplifier and the calibration voltage Vcal.

Abstract: There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.

Abstract: Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section.

Abstract: Provided is a test apparatus that tests a device under test, having two operational modes which are (i) an edge strobe mode in which the test apparatus judges acceptability of a value of an output signal from the device under test at sequentially designated reference timings, based on expected value information, and (ii) a multi-strobe mode in which the test apparatus judges the acceptability of values of the output signal at a plurality of strobes for each reference timing, based on expected value information, the plurality of strobes being generated based on the reference timing, and comprising a conversion control section that converts an expected value pattern supplied thereto into expected value information to be used in the edge strobe mode or into expected value information to be used in the multi-strobe mode, depending on which of the edge strobe mode and the multi-strobe mode is selected.

Abstract: Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section.

Abstract: There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.

Abstract: A receiving apparatus that acquires a reception signal using a recovered clock that is recovered from an edge of the reception signal. The receiving apparatus comprises a recovered clock generating section that generates the recovered clock; a multi-strobe generating section that generates a plurality of strobes having different phases from each other, according to a pulse of the recovered clock; a detecting section that detects an edge position of the reception signal relative to the strobes, based on a value of the reception signal at timings of each of the strobes; an adjusting section that adjusts a phase of the recovered clock according to the edge position of the reception signal; and an acquiring section that acquires the reception signal at a timing shifted by a set phase difference, which is set in advance, from the recovered clock.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: A test apparatus includes a bus switch unit capable of switching the output ports to select which of the output ports an input signal is output from, a control unit for inputting a plurality of control signals, according to a test program for testing the electronic device, to the bus switch unit and controlling which of the output ports each of the control signals is output from, a plurality of slots provided corresponding to the plurality of output ports, and a device interface capable of switching the connectors, which couple the plurality of slots and the electronic device, to select which of the connectors the slot is coupled to, wherein the device interface further includes a diagnosis decoder for sequentially supplying each of the test modules with a diagnosis signal via each of the connectors, and the control unit detects which of the test modules the diagnosis signal received via each of the connectors is supplied to and which of the connectors each of the output ports is coupled to based on a result

Abstract: Provided is a test apparatus that tests a device under test, having two operational modes which are (i) an edge strobe mode in which the test apparatus judges acceptability of a value of an output signal from the device under test at sequentially designated reference timings, based on expected value information, and (ii) a multi-strobe mode in which the test apparatus judges the acceptability of values of the output signal at a plurality of strobes for each reference timing, based on expected value information, the plurality of strobes being generated based on the reference timing, and comprising a conversion control section that converts an expected value pattern supplied thereto into expected value information to be used in the edge strobe mode or into expected value information to be used in the multi-strobe mode, depending on which of the edge strobe mode and the multi-strobe mode is selected.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.