Patents by Inventor Nobuhiro Imaizumi
Nobuhiro Imaizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10283434Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.Type: GrantFiled: October 20, 2016Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
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Patent number: 10062658Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.Type: GrantFiled: July 6, 2015Date of Patent: August 28, 2018Assignee: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Patent number: 10056342Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.Type: GrantFiled: October 31, 2012Date of Patent: August 21, 2018Assignee: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Patent number: 9911642Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.Type: GrantFiled: August 6, 2014Date of Patent: March 6, 2018Assignee: FUJITSU LIMITEDInventors: Taiji Sakai, Nobuhiro Imaizumi
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Patent number: 9853014Abstract: An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface; a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity; a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.Type: GrantFiled: September 26, 2016Date of Patent: December 26, 2017Assignee: FUJITSU LIMITEDInventors: Ryo Kikuchi, Nobuhiro Imaizumi, Hiroshi Onuki
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Patent number: 9754904Abstract: An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.Type: GrantFiled: July 18, 2016Date of Patent: September 5, 2017Assignee: FUJITSU LIMITEDInventors: Masaru Morita, Nobuhiro Imaizumi
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Publication number: 20170125359Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.Type: ApplicationFiled: October 20, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
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Publication number: 20170098631Abstract: An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface;a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity;a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.Type: ApplicationFiled: September 26, 2016Publication date: April 6, 2017Applicant: FUJITSU LIMITEDInventors: Ryo Kikuchi, Nobuhiro IMAIZUMI, Hiroshi Onuki
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Publication number: 20170047302Abstract: An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.Type: ApplicationFiled: July 18, 2016Publication date: February 16, 2017Applicant: FUJITSU LIMITEDInventors: Masaru Morita, Nobuhiro Imaizumi
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Publication number: 20160354871Abstract: A flux includes: a first glycol-based polyhydric alcohol having a molecular weight of 300 or less; and a second glycol-based polyhydric alcohol having a molecular weight of 600 or more.Type: ApplicationFiled: April 13, 2016Publication date: December 8, 2016Applicant: FUJITSU LIMITEDInventors: KOZO SHIMIZU, Seiki Sakuyama, Nobuhiro Imaizumi
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Publication number: 20160228999Abstract: A flux used for bonding a solder includes: 75 wt % or more of ethylene glycol polymer represented by the following formula: HO(CH2CH2O)nH [n is an integer of 4 or more], wherein an evaporation of the ethylene glycol polymer while being heated is terminated at a temperature equal to or greater than a bonding temperature of the solder.Type: ApplicationFiled: December 29, 2015Publication date: August 11, 2016Applicant: FUJITSU LIMITEDInventors: Kozo Shimizu, Nobuhiro Imaizumi, Seiki Sakuyama
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Patent number: 9235001Abstract: An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip.Type: GrantFiled: April 15, 2015Date of Patent: January 12, 2016Assignee: FUJITSU LIMITEDInventors: Shigeaki Sekiguchi, Nobuhiro Imaizumi, Toshiya Akamatsu, Shinji Tadaki, Akinori Hayakawa
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Publication number: 20150323738Abstract: An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip.Type: ApplicationFiled: April 15, 2015Publication date: November 12, 2015Inventors: Shigeaki Sekiguchi, Nobuhiro Imaizumi, Toshiya Akamatsu, Shinji Tadaki, Akinori Hayakawa
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Publication number: 20150311171Abstract: A surface of a connection terminal of an electronic component is covered with a protection layer made of a AgSn alloy. The electronic component is soldered to a connection terminal of a circuit board.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Applicant: FUJITSU LIMITEDInventors: Seiki SAKUYAMA, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Patent number: 9082756Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: GrantFiled: March 26, 2014Date of Patent: July 14, 2015Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
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Patent number: 8922027Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.Type: GrantFiled: November 8, 2012Date of Patent: December 30, 2014Assignee: Fujitsu LimitedInventors: Taiji Sakai, Nobuhiro Imaizumi
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Publication number: 20140342504Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.Type: ApplicationFiled: August 6, 2014Publication date: November 20, 2014Applicant: FUJITSU LIMITEDInventors: Taiji SAKAI, Nobuhiro IMAIZUMI
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Patent number: 8860232Abstract: According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.Type: GrantFiled: November 8, 2012Date of Patent: October 14, 2014Assignee: Fujitsu LimitedInventors: Taiji Sakai, Nobuhiro Imaizumi
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Publication number: 20140203444Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: FUJITSU LIMITEDInventors: KOZO SHIMIZU, KEISHIRO OKAMOTO, NOBUHIRO IMAIZUMI, TADAHIRO IMADA, KEIJI WATANABE
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Patent number: 8728867Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: GrantFiled: January 23, 2012Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe