Patents by Inventor Nobuhiro Minami

Nobuhiro Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9552619
    Abstract: An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: January 24, 2017
    Assignees: MegaChips Corporation, Nikon Corporation
    Inventors: Shogo Iwai, Kazuma Takahashi, Nobuhiro Minami, Kensuke Uchida, Toru Miyakoshi
  • Patent number: 8743132
    Abstract: A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 3, 2014
    Assignee: MegaChips Corporation
    Inventor: Nobuhiro Minami
  • Publication number: 20140043343
    Abstract: An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part.
    Type: Application
    Filed: April 1, 2013
    Publication date: February 13, 2014
    Applicants: Nikon Corporation, MegaChips Corporation
    Inventors: Shogo IWAI, Kazuma TAKAHASHI, Nobuhiro MINAMI, Kensuke UCHIDA, Toru MIYAKOSHI
  • Patent number: 8369634
    Abstract: A sorting unit sorts a plurality of data sets of HP component having been processed by a decoding unit, selectively employing one of a first table corresponding to a first orientation of prediction and a second table corresponding to a second orientation of prediction in accordance with an orientation of prediction of HP component. The sorting unit includes an inverse prediction unit performing inverse prediction on data of LP component inputted from the decoding unit, a processing unit obtaining an orientation of prediction of HP component, based on the data of LP component after inverse prediction by the inverse prediction unit, and a selecting unit selecting one of the first and second tables, based on the orientation of prediction of HP component obtained by the processing unit.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 5, 2013
    Assignee: MegaChips Corporation
    Inventors: Nobuhiro Minami, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Masahiro Moriyama, Hiromu Hasegawa
  • Patent number: 8160376
    Abstract: An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: April 17, 2012
    Assignee: MegaChips Corporation
    Inventors: Masahiro Moriyama, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Hiromu Hasegawa
  • Patent number: 8160377
    Abstract: A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: April 17, 2012
    Assignee: MegaChips Corporation
    Inventors: Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Patent number: 8107746
    Abstract: A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 31, 2012
    Assignee: MegaChips Corporation
    Inventors: Hideki Daian, Yujiro Tani, Yusuke Mizuno, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20110161574
    Abstract: A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 30, 2011
    Applicant: MEGACHIPS CORPORATION
    Inventor: Nobuhiro MINAMI
  • Publication number: 20100128999
    Abstract: A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient.
    Type: Application
    Filed: March 23, 2009
    Publication date: May 27, 2010
    Applicant: MegaChips Corporation
    Inventors: Yujiro TANI, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20100111430
    Abstract: A sorting unit sorts a plurality of data sets of HP component having been processed by a decoding unit, selectively employing one of a first table corresponding to a first orientation of prediction and a second table corresponding to a second orientation of prediction in accordance with an orientation of prediction of HP component. The sorting unit includes an inverse prediction unit performing inverse prediction on data of LP component inputted from the decoding unit, a processing unit obtaining an orientation of prediction of HP component, based on the data of LP component after inverse prediction by the inverse prediction unit, and a selecting unit selecting one of the first and second tables, based on the orientation of prediction of HP component obtained by the processing unit.
    Type: Application
    Filed: October 2, 2009
    Publication date: May 6, 2010
    Applicant: MegaChips Corporation
    Inventors: Nobuhiro MINAMI, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20100104206
    Abstract: An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream.
    Type: Application
    Filed: March 23, 2009
    Publication date: April 29, 2010
    Applicant: MegaChips Corporation
    Inventors: Masahiro Moriyama, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Hiromu Hasegawa
  • Publication number: 20100086223
    Abstract: A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits.
    Type: Application
    Filed: March 17, 2009
    Publication date: April 8, 2010
    Applicant: MegaChips Corporation
    Inventors: Hideki DAIAN, Yujiro Tani, Yusuke Mizuno, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Patent number: 7616809
    Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: November 10, 2009
    Assignee: MegaChips LSI Solutions Inc.
    Inventors: Takashi Matsutani, Satoru Kubota, Nobuhiro Minami
  • Patent number: 7570288
    Abstract: A pixel signal of Bayer pattern output from an imaging device is subjected to interpolation in a pixel interpolation circuit, and converted into a YCbCr signal in a color space conversion circuit. A chroma value calculation circuit calculates a chroma value based on the pixel signal output from the imaging device. A look-up table converts the chroma value into a suppression signal. More specifically, when the chroma value is lower than a threshold value, the look-up table outputs a value lower than 1 as the suppression signal. The suppression signal is corrected in another look-up table, and then, works on Cr and Cb signals in multipliers. A signal in a low-chroma region is thereby suppressed.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: August 4, 2009
    Assignee: MegaChips LSI Solutions Inc.
    Inventors: Hiromu Hasegawa, Munehiro Mori, Nobuhiro Minami
  • Patent number: 7539352
    Abstract: A first pixel group containing a pixel of interest, a second pixel group containing the first pixel group, and a third pixel group containing the second pixel group are defined. A first reference pixel value is calculated based on the first pixel group, and a second reference pixel value is calculated based on the third pixel group. The second pixel group is divided into two sub-groups with respect to the second reference pixel value. The sub-group containing the pixel of interest is selected as a target set. In the target set, a pixel with a pixel value close to the first reference pixel value is selected as a corrective pixel. The pixel value of the pixel of interest is replaced with the pixel value of the corrective pixel.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: May 26, 2009
    Assignee: MegaChips LSI Solutions Inc.
    Inventors: Hiromu Hasegawa, Munehiro Mori, Nobuhiro Minami
  • Publication number: 20070248263
    Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.
    Type: Application
    Filed: August 4, 2006
    Publication date: October 25, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Takashi Matsutani, Satoru Kubota, Nobuhiro Minami
  • Publication number: 20060262196
    Abstract: A pixel signal of Bayer pattern output from an imaging device is subjected to interpolation in a pixel interpolation circuit, and converted into a YCbCr signal in a color space conversion circuit. A chroma value calculation circuit calculates a chroma value based on the pixel signal output from the imaging device. A look-up table converts the chroma value into a suppression signal. More specifically, when the chroma value is lower than a threshold value, the look-up table outputs a value lower than 1 as the suppression signal. The suppression signal is corrected in another look-up table, and then, works on Cr and Cb signals in multipliers. A signal in a low-chroma region is thereby suppressed.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 23, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Hiromu HASEGAWA, Munehiro Mori, Nobuhiro Minami
  • Publication number: 20060159361
    Abstract: A first pixel group containing a pixel of interest, a second pixel group containing the first pixel group, and a third pixel group containing the second pixel group are defined. A first reference pixel value is calculated based on the first pixel group, and a second reference pixel value is calculated based on the third pixel group. The second pixel group is divided into two sub-groups with respect to the second reference pixel value. The sub-group containing the pixel of interest is selected as a target set. In the target set, a pixel with a pixel value close to the first reference pixel value is selected as a corrective pixel. The pixel value of the pixel of interest is replaced with the pixel value of the corrective pixel.
    Type: Application
    Filed: December 27, 2005
    Publication date: July 20, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Hiromu Hasegawa, Munehiro Mori, Nobuhiro Minami
  • Patent number: 6932937
    Abstract: Apparatus for manufacturing a molded article having a substrate material and skin material may include a first die that receives and supports the substrate material and a second die that receives and supports the skin material. The first die is arranged and constructed to engage the first die. A cutter may be provided on the first molding die. The cutter can be actuated when the second die moves toward the first die in order to partially cut away the substrate material.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: August 23, 2005
    Assignee: Araco Kabushiki Kaisha
    Inventors: Nobuhiro Minami, Tamotsu Nagaya
  • Publication number: 20020125616
    Abstract: Apparatus for manufacturing a molded article having a substrate material and skin material may include a first die that receives and supports the substrate material and a second die that receives and supports the skin material. The first die is arranged and constructed to engage the first die. A cutter may be provided on the first molding die. The cutter can be actuated when the second die moves toward the first die in order to partially cut away the substrate material.
    Type: Application
    Filed: March 5, 2002
    Publication date: September 12, 2002
    Inventors: Nobuhiro Minami, Tamotsu Nagaya