Abstract: A reference potential vr is applied to the gate of an NMOSFET 1a, and a potential Vn at a node N3 connected to an end of a reference resistor 5 is applied to the gate of an NMOSFET 1b. A PMOSFET 4 in series with the reference resistor 4 and a PMOSFET 4 forms a current mirror circuit. A load circuit 9 is connected in series with a PMOSFET 8 which forms a mirror circuit in combination with the PMOSFET 4. When the potential Vn is higher than the reference potential Vr, the source-drain conductance of the PMOSFET 1a increases, and the potential at the gate of the PMOSFET 4 rises, causing the current flowing through the PMOSFET 4 to decrease, and the potential Vn at the node N3 is lowered. The configuration of the circuit is simplified, and the response speed is increased.

Abstract: A switch circuit includes an input terminal, an internal circuit, and first and second MOS transistors. The input terminal receives an input signal. The internal circuit executes a predetermined function. The first MOS transistor is a first conductivity type MOS transistor. The first MOS transistor is coupled between the input terminal and the internal circuit, and has a control gate receiving a control signal, a first electrode coupled to the input terminal and a second electrode. The second MOS transistor is a second conductivity type MOS transistor of a type opposite the first conductivity type MOS transistor. The second MOS transistor is coupled between the input terminal and the internal circuit, and has a control gate receiving a signal having a phase opposite the control signal, a first electrode coupled to the second electrode of the first MOS transistor and a second electrode coupled to the internal circuit.

Abstract: The wrong operation preventing circuit is supplied for preventing such accidents as destruction of data, a memory cell section, a sense amplifier and a operation judgement section. The memory cell section is placed at a furthest position from the sense amplifier, the sense amplifier detects the change of voltage on bit line, and the operation judgement section monitors the output of the sense amplifier and outputs a signal for controlling whether the CPU needs to reset.

Abstract: A switch circuit includes an input terminal which receives an input signal and an internal circuit which executes a predetermined function. The switch circuit also includes a first switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving a control signal, a first electrode coupled to the input terminal, and a second electrode. The switch circuit also includes a second switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving the control signal, a first electrode coupled to the second electrode of the first switch element, and a second electrode coupled to the internal circuit.

Abstract: The wrong operation preventing circuit is supplied for preventing such accidents as destruction of data and the like, comprising a memory cell section, a sense amplifier and a operation judgement section. The memory cell section is placed at a furthest position from the sense amplifier, the sense amplifier detects the change of voltage on bit line, and the operation judgement section monitors the output of the sense amplifier and outputs a signal for controlling whether the CPU needs to reset.

Abstract: A semiconductor integrated-circuit device includes both conventional internal circuitry, and a selection circuit that provides external output of signals from the internal circuitry under control of a selection signal. In a parallel test system, the output terminals of a plurality of devices under test are connected to a single set of tester input terminals, at which response signals are received from each device in turn. Alternatively, each device has an internal test circuit that carries out tests in response to test control codes received from a tester, evaluates the response signals from the internal circuitry, makes a pass/fail decision, and provides the tester with the pass/fail result.

Abstract: A charge pump circuit 203 boosts a power supply voltage to generate a high voltage VPP in response to clocks CK, CK/ supplied from an oscillation circuit 202. A voltage detecting circuit 205 discriminates whether the high voltage VPP reaches a desired voltage value or not and represents it by discrimination signals LVPP, DIS/. If the high voltage VPP does not reach the desired voltage value, a writing control circuit 201 stops the oscillation circuit 202 from effecting its oscillating operation and stops the charge pump circuit 203 from boosting the power supply voltage to the high voltage VPP in response to the discrimination signal DIS/. Accordingly, the high voltage VPP having a desired voltage value is not applied to a memory cell of a memory circuit 204 so that writing is not effected. Further, the discrimination signal LVPP, is outputted externally so as to represent the writing state in the memory cell.

Abstract: An IC card having means for protecting erroneous operation. A circuit for detecting incomplete contact is provided.

Abstract: In a nonvolatile memory device or a microcomputer with a nonvolatile memory, data errors arising from loss of charge in the floating gates of memory cells are detected and corrected by applying two different sense voltages to the memory cells and comparing the outputs. Instead of using a cumbersome error-correcting code, this error-correcting scheme requires only one parity bit per word, yet it can detect and correct errors in any odd number of bits. Benefits include reduced chip size and longer life for electrically erasable and programmable memories.