Patents by Inventor Nobuhito Suzuya
Nobuhito Suzuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11756918Abstract: A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.Type: GrantFiled: February 24, 2021Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Tsutomu Sano, Kazuya Maruyama, Satoru Takaku, Nobuhito Suzuya
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Publication number: 20230110997Abstract: According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.Type: ApplicationFiled: August 26, 2022Publication date: April 13, 2023Inventors: Yasuo OTSUKA, Nobuhito SUZUYA
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Publication number: 20210288018Abstract: A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.Type: ApplicationFiled: February 24, 2021Publication date: September 16, 2021Inventors: Tsutomu SANO, Kazuya MARUYAMA, Satoru TAKAKU, Nobuhito SUZUYA
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Patent number: 8633602Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.8a4 a1: a logarithm of the modulus of elasticity [MPa] of the adhesive layer a2: the sink amount [mm] of the adhesive layer a3: the thickness [mm] of the protective film a4: a logarithm of the modulus of elasticity [MPa] of the protective film.Type: GrantFiled: March 15, 2012Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Atsushi Yoshimura, Hideko Mukaida
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Publication number: 20120326339Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.Type: ApplicationFiled: March 15, 2012Publication date: December 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Nobuhito SUZUYA, Atsushi Yoshimura, Hideko Mukaida
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Patent number: 7397132Abstract: Disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package mounted on another surface of the organic material substrate in a manner to avoid a position opposing to the flip chip connected semiconductor chip. Additionally, disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package having a connection terminal and mounted on another surface of the organic material substrate via the connection terminal in a manner that an overlap with the flip chip connected semiconductor chip occurs, at least a part of the connection terminal in the overlap being a dummy terminal not used for transmission of an electric signal.Type: GrantFiled: March 13, 2006Date of Patent: July 8, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Nobuhito Suzuya
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Publication number: 20060202350Abstract: Disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package mounted on another surface of the organic material substrate in a manner to avoid a position opposing to the flip chip connected semiconductor chip. Additionally, disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package having a connection terminal and mounted on another surface of the organic material substrate via the connection terminal in a manner that an overlap with the flip chip connected semiconductor chip occurs, at least a part of the connection terminal in the overlap being a dummy terminal not used for transmission of an electric signal.Type: ApplicationFiled: March 13, 2006Publication date: September 14, 2006Inventor: Nobuhito Suzuya
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Patent number: 6666380Abstract: A non-contact IC card comprises: a substantially rectangular insulating substrate; a semiconductor chip mounted on a first face of the insulating substrate; and an antenna coil for transmitting information and for enhancing the mechanical strength of the insulating substrate, the antenna coil being arranged on the first face of the insulating substrate along the outer periphery of the first face, and the antenna coil having first and second connecting terminals which are connected to the semiconductor chip. Thus, it is possible to provide a non-contact IC card capable of enhancing the connection reliability of an IC chip mounting portion, maintaining communication characteristics, and maintaining a high mechanical strength.Type: GrantFiled: September 14, 2000Date of Patent: December 23, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Nobuhito Suzuya
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Patent number: 6326243Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.Type: GrantFiled: December 31, 1997Date of Patent: December 4, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida
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Patent number: 5753969Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.Type: GrantFiled: August 14, 1996Date of Patent: May 19, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida